Bit line segmenting in random access memories

Details Bit line segmenting in random access memories Bit line segmenting in random access memories

2005-06-07

2005-06-07

Kim, Hong (Department: 2186)

Static information storage and retrieval

Read/write circuit

C365S189030, C365S203000, C365S230030

Reexamination Certificate

active

06903982

ABSTRACT:
An integrated memory circuit and corresponding method for segmenting bit lines are provided, where the integrated memory circuit includes a sense amplifier, a layered bit line in signal communication with the sense amplifier, several segment pass transistors in signal communication with the layered bit line, several segmented bit lines, each in signal communication with a corresponding one of the several segment pass transistors, respectively, several memory cell pass transistors in signal communication with one of the several segmented bit lines, and a plurality of memory cell capacitors, each in signal communication with a corresponding one of the plurality of memory cell transistors, respectively; and where the corresponding method for segmenting bit lines includes receiving a memory cell address, activating a memory cell pass transistor with a wordline corresponding to the memory cell address, receiving a signal indicative of the memory cell charge level on a segmented bit line through the memory cell transistor, activating a segment pass transistor corresponding to the memory cell address, receiving a signal indicative of the memory cell charge level on a layered bit line through the segment pass transistor, and receiving a signal indicative of the memory cell charge level at the sense amplifier through the layered bit line.

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IBM Technical Disclosure Bulletin, Dec. 1988, “Fully-Divided Bit Line for Dynamic Random-Access Memory Sensing Circuitry”, vol. No.: 31, Issue No.: 7, p. No.: 266-272.

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