Bit line reset circuit of memory

Details Bit line reset circuit of memory Bit line reset circuit of memory

1998-05-07

2000-02-15

Nelms, David

Static information storage and retrieval

Read/write circuit

For complementary information

36518908, G11C 700

Patent

active

060260343

ABSTRACT:
Switching transistors 20, 22, 22P, 21, 23 and 23P and a portion of control circuit for transistors 20 and 21 constitutes a bit line reset circuit on memory cell side. In reading `H` from the memory cell connected to a bit line BLC or *BLC, the both bit lines are set at a higher reset potential Vii, while in reading `L`, the both bit lines are reset at a lower reset potential Vss. Transfer gates 10 and 11 are turned off before sufficient amplification of a potential difference between the bit lines BL and *BL. The operation of restoring into a memory cell read destructively from is performed in parallel with the operation of bit line reset.

REFERENCES:
patent: 5222041 (1993-06-01), Nishimori et al.
patent: 5761122 (1998-06-01), Nakamura et al.

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