Bit line reference circuit for a nonvolatile semiconductor memor

Details Bit line reference circuit for a nonvolatile semiconductor memor Bit line reference circuit for a nonvolatile semiconductor memor

1996-07-26

1998-06-23

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular connection

36518529, G11C 1134

Patent

active

057711925

ABSTRACT:
A bit line reference circuit for a nonvolatile semiconductor memory device performs a referenced data access operation using a single bit line having upper and lower portions. The circuit has an open bit line structure and includes an upper memory cell string connected to the upper portion of the bit line, and a lower memory cell string connected to the lower portion of the bit line. An upper reference cell string is connected to the upper bit line for providing a reference potential to the upper bit line in response to a first control signal, while the lower memory cell string is selected. A lower reference cell string is connected to the lower bit line for providing a reference potential to the lower bit line in response to a second control signal, while the upper memory cell string is selected. A page buffer is connected between the upper and lower portions of the bit line and accesses data by comparing the potentials on the upper and lower portions of the bit line. Each reference cell string includes two transistors connected in series between the respective portion of the bit line and ground. The reference cell transistors are fabricated with the same process and structure as the transistors in the memory cell strings. The control gate and floating gate of each memory cell transistor are electrically coupled with an abutting contact.

REFERENCES:
patent: 5253210 (1993-10-01), Terada
patent: 5299162 (1994-03-01), Kim et al.
patent: 5541879 (1996-07-01), Suh et al.
patent: 5548146 (1996-08-01), Kuroda et al.

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