Bit-line drive circuit for a semiconductor memory

Details Bit-line drive circuit for a semiconductor memory Bit-line drive circuit for a semiconductor memory

1993-04-28

1995-03-14

Harvey, Jack B.

Static information storage and retrieval

Systems using particular element

Semiconductive

3652256, G11C 1134

Patent

active

053982010

ABSTRACT:
A circuit technique suitable to attain a high speed of a memory which is constructed in a manner such that memory cells include a field effect transistor and peripheral circuits include a bipolar transistor and a field effect transistor. According to the invention, a bipolar transistor whose collector is connected to a differential amplifier and which supplies a current to the differential amplifier in accordance with a signal which is inputted to a base or an emitter is added, and a bipolar transistor to supply a current only when writing to bit lines is connected. According to the invention, a high speed of the access time when information is read out by switching the selection bit line is accomplished. Further, the charge/discharge time of the bit line when information is written is reduced and a high speed of the writing time can be also accomplished. The improvement of the drivers of word lines and bit lines is also disclosed and a semiconductor memory which can operate at a high speed as a whole semiconductor memory can be realized.

REFERENCES:
patent: 4785422 (1988-11-01), Berndt et al.
patent: 4961168 (1990-10-01), Tran
patent: 5091879 (1992-02-01), Tran
patent: 5099452 (1992-03-01), Yamakoshi et al.
patent: 5111435 (1992-05-01), Miyamoto
Tran et al, "An 8ns BiCMOS 1Mb ECL SRAM with a Configurable Memory Array Size", IEEE International Solid-State Circuit Conference, Feb. 15, 1989, pp. 36-37.

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