Bit line control and sense amplification for TCCT-based...

Details Bit line control and sense amplification for TCCT-based... Bit line control and sense amplification for TCCT-based...

2005-10-25

2005-10-25

Tran, M. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Negative resistance

C365S203000

Reexamination Certificate

active

06958931

ABSTRACT:
A circuit and a method are provided for facilitating control of bit lines in preparation for, or during, sense amplification of data signals from thinly capacitively-coupled thyristor (“TCCT”)-based memory cells. In accordance with a specific embodiment, a circuit and method are designed, among other things, to effectively minimize power consumption by memory cells and to increase speed and reliability of sense amplification. In another specific embodiment, the circuit and method are directed to TCCT-based memory cells.

REFERENCES:
patent: 6229161 (2001-05-01), Nemati et al.
patent: 6611452 (2003-08-01), Han
Barth, Anand, Dreibelbis, Nelson; “A 300 MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-line Twisting and Direct Reference Cell Write,” 2002 IEEE International Solid-State Circuits Conference.
Kang, Kye, Lee, Park, Kim, Lee, Hong, Park, Chung; “A Hierarchy Bitline Boost Scheme forSub-1.5V Operation and Short Precharge Time on High Density FeRAM,” 2002 IEEE International Solid-State Circuits Conference.
Nishihara, Ito; “A Quasi-Matrix Ferroelectric Memory for Future Silicon Storage,” 2002 IEEE International Solid-State Circuits Conference.
Choi, Geon, Jang, Min, Song, Lee, Kim, Jung, Joo, Kim; “A 0.25 um 3.0V 1T1C 32Mb Nonvolatile Ferroelectric RAM with Address Transition Detector (ATD) and Current Forcing Latch Sense Amplifier (CFLSA) Scheme,” 2002 IEEE International Solid-State Conference.

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