Bit line control and sense amplification for TCCT-based...

Details Bit line control and sense amplification for TCCT-based... Bit line control and sense amplification for TCCT-based...

2002-07-05

2004-04-13

Tran, Michael (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S190000

Reexamination Certificate

active

06721220

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, and in particular, to a circuit and a method for facilitating the control of bit lines in preparation for, or during, sense amplification of data signals from thinly capacitively-coupled thyristor (“TCCT”)-based memory cells.
2. Description of Related Art
Random Access Memories (“RAM”) are memories capable of multiple read-write cycles and are widely used to temporally store data in computing applications. A typical RAM is structured to include numerous memory cells arranged in an array of rows and columns wherein each memory cell is designed to store a datum or unit of data as a binary digit (i.e., a binary zero or a binary one). Each row of the memory cell array is typically connected to a word line and each column of the memory cell array is typically connected to a bit line (or a pair of complementary bit lines in some memories, such as an SRAM-based memory). The typical RAM structure also includes other circuitry to effect traditional read and write operations, such as reference signal generation circuitry, control signal circuitry, and sensing circuitry.
A constituent memory cell for a RAM is disclosed in U.S. Pat. No. 6,229,161 issued to Nemati et al., which is incorporated herein by reference in its entirety. Netmati et al. discloses capacitively coupled NDR devices for use as SRAM memory cells (also referred herein as TRAM cells). The cells disclosed by Nemati et al. are hereinafter referred to as thinly capacitively coupled thyristor (“TCCT”)-based memory cells wherein the NDR device is a TCCT device.
FIG. 1
shows a pair of representative TCCT-based memory cells
10
as disclosed by Nemati et al., and
FIG. 2
shows a cross-section through one of the pairs of TCCT-based memory cell
10
along the line
2
—
2
.
FIG. 3
shows a schematic circuit diagram corresponding to the TCCT-based memory cell illustrated in
FIGS. 1 and 2
. The TCCT-based memory cell
10
includes an NDR device
12
and a pass transistor
14
. A charge-plate or gate-like device
16
is disposed adjacent to, and in the case of the illustrated embodiment, surrounding, the NDR device
12
. A P+ region
18
of the NDR device
12
is connected to a metallization layer
20
so that a first voltage V
1
, such as V
DDA
, can be applied to the NDR device
12
through the P+ region
18
. An N+ region of the NDR device
12
forms a storage node
22
that is connected to a source of the pass transistor
14
.
Successive TCCT-based memory cells
10
are joined by three lines, a bit line
26
, a first word line (WL
1
)
28
, and a second word line (WL
2
)
30
. The bit line
26
connects a drain
32
of pass transistor
14
to successive TCCT-based memory cells
10
. In a similar fashion, pass transistor
14
includes a gate
34
that forms a portion of the first word line
28
. Likewise, the gate-like device
16
forms a portion of the second word line
30
.
TCCT-based memory cell
10
has both an “on” state and an “off” state. In the “on” state TCCT-based memory cell
10
generates a current that is received by bit line
26
. In the “off” state TCCT-based memory cell
10
produces essentially no current. Second word line
30
is configured to write a state to the TCCT-based memory cell
10
, while first word line
28
is generally configured to read the state of the TCCT-based memory cell
10
.
An inherent characteristic of TCCT-based memory cell
10
is that the NDR device
12
can develop a leakage current (“I
LEAK
”) when voltage V
1
(e.g., V
DDA
) is applied thereto. I
LEAK
typically is generated in stand-by mode when some TCCT-based cells are accessed for a read or write operation while other TCCT-based cells are not. When the WL
2
line is coupled to both a cell that is being accessed and to a cell that is not, I
LEAK
will be generated by the non-accessed cell. In particular, when an active WL
2
signal is applied to the non-selected NDR device
12
, the non-selected pass transistor
14
provides a path from the pass transistor's source terminal to its drain terminal. In this instance, I
LEAK
flows from NDR device
12
through both node “N”
40
and pass transistor
14
to bit line
26
. Generally, one or more circuits connected to bit line
26
provide a path to ground, where such circuits typically can include a bit line pre-charge circuit, a signal sensing circuit, or other like circuitry.
Signal sensing circuits are commonly employed to sense or detect a low-level data signal voltage (or current) from a memory cell and then amplify it to a specific signal level, such as a value of the voltage (or current) representing a logical one (e.g., V
DDA
) or zero (e.g., ground). A sense amplifier is one such sensing circuit designed to receive the data signal and a reference signal, and thereafter, resolve the data signal into a logical one or zero.
A drawback of using traditional bit line control techniques in conventional sense amplification is that excess charge is not sufficiently removed from the bit lines and sense amplifier nodes to overcome sense amplification errors. Such errors are typical exacerbated by temperature fluctuations, noise, device mismatch and like factors. Since TCCT-based memory cells provide data signals with very small voltages (e.g., 200 mV) for sense amplification, insufficient removal of excess charge can lead to sensing errors.
Another drawback of using traditional bit line control techniques and circuits is that a collective I
LEAK
in a memory device decreases power efficiency. Memory devices are designed to include one or more memory arrays, each memory array having numerous bit lines. In turn, each bit line can have more than one TCCT-based memory cells coupled to the bit line. For example, each bit line in a single or open bit line memory architecture can have thirty-two to more than a thousand TCCT-based memory cells coupled thereto. As the number of TCCT-based memory cells connected to the bit line increases, I
LEAK
increases proportionately. Hence, as I
LEAK
increases, the power consumed also increases. Moreover, as constituent device size (i.e., channel width) of NDR devices of TCCT-based memory cells continue to decrease, the associated I
LEAK
contribution from each individual memory cell increases. Conventional sensing circuits and bit line control techniques are thus not designed to minimize power consumption by TCCT-based memory cells during, for example, stand-by mode.
SUMMARY OF THE INVENTION
There is a need to overcome the aforementioned drawbacks of conventional sensing circuits and bit line control techniques to minimize power consumption by memory cells, such as TCCT-based memory cells, and to increase speed and reliability of sense amplification. The present invention provides for a circuit and a method for facilitating control of bit lines in preparation for, or during, sense amplification of data signals generated by TCCT-based memory cells. In accordance with a specific embodiment of the present invention, a sensing circuit includes a sense amplifier to resolve a data signal generated by a memory cell. The sensing circuit comprises a bit line coupled to the memory cell to receive the data signal, a first node connected to a first input of the sense amplifier. The first node is configured to couple with the bit line. A first pre-charge device is coupled to the bit line to pre-charge the bit line to a first predetermined level. Lastly, the circuit includes a second pre-charge device coupled to the first node to pre-charge the bit line to a second pre-determined level.
In another embodiment, a method provides control of a sensing circuit, where the method includes floating a bit line, pre-charging a first node to a first pre-determined level, pre-charging the bit line to a second pre-determined level, and coupling the bit line to the first node, the first node associated with a first sense amplifier input.


REFERENCES:
patent: 5274598 (1993-12-01), Fujii et al.
patent: 5448516 (1995-09-01), Tsukikawa et al.
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