Bit line conditioning circuit for random access memory

Details Bit line conditioning circuit for random access memory Bit line conditioning circuit for random access memory

1994-11-29

1996-11-05

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Complementing/balancing

365203, G11C 700

Patent

active

055724736

ABSTRACT:
A bit line conditioning circuit for a random access memory (RAM) is provided. A pair of driver transistors maintain the bit line and bit line inverse at a high voltage before a memory cell is accessed. When a memory cell is accessed, the driver transistors are turned off such that the memory cell is accessed when the bit line and bit line inverse are not statically loaded. Since the bit line and bit line inverse are not statically loaded when the access is initiated, a read or write operation occurs more quickly than in a prior art RAM. An equalization transistor is coupled across the bit line and bit line inverse, and is turned on when a memory access is initiated to equalize the value over the bit line and bit line inverse.

REFERENCES:
patent: 4658381 (1987-04-01), Reed et al.
patent: 4813022 (1989-03-01), Matsui et al.
patent: 4893278 (1990-01-01), Ito
patent: 5047985 (1991-09-01), Miyaji
patent: 5091889 (1992-02-01), Hamano et al.
patent: 5233560 (1993-08-01), Foss et al.
patent: 5355343 (1994-10-01), Shu et al.

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