Bit line charge sensing apparatus having CMOS threshold voltage

Details Bit line charge sensing apparatus having CMOS threshold voltage Bit line charge sensing apparatus having CMOS threshold voltage

1987-03-30

1989-08-15

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365203, 365190, 365207, 365154, 307530, G11C 700, G11C 1100

Patent

active

048581950

ABSTRACT:
An apparatus for sensing an electric charge appearing on at least one bit line of a memory cell comprises a pair of P-channel MOS (Metal Oxide Semiconductor) transistors whose sources are commonly connected, a pair of N-channel MOS (Metal Oxide Semiconductor) transistors whose sources are commonly connected, both pairs of the PMOS and NMOS transistors carrying out latch operations according to control signals supplied to their sources to sense the electric charge appearing on either a first or second bit line. In at least one of the pairs of PMOS and NMOS transistors, the gate of each MOS transistor is connected to either the first or second bit line via a capacitor, a first switching element is disposed between the drain of each MOS transistor and gate thereof, and a second switching element is disposed between the drain of each MOS transistor and a junction to either the first or second bit line. When control voltages applied to both sources of the PMOS transistors and NMOS transistors are changed and the switching elements are switched over during a precharge interval and sensing operation interval, the capacitors store voltages according to the respective threshold voltages of the PMOS and NMOS transistors so that divergence in the threshold voltages can be compensated for.

REFERENCES:
patent: 4355377 (1982-10-01), Sud et al.
patent: 4408303 (1983-10-01), Guterman et al.
patent: 4494221 (1985-01-01), Hardee et al.
patent: 4532609 (1985-07-01), Iizuka
patent: 4547685 (1985-10-01), Wong
patent: 4802128 (1989-01-01), Watanabe et al.
IBM Technical Disclosure Bulletin, vol. 20, No. 1, Jun. 77, pp. 268-269; "Small Charge Sense Latch", by Cassidy et al.
IBM Tech. Discl. Bull., vol. 23, No. 7A, Dec. 80, pp. 3037-3038, "Sense Amp. W resistive Decoupling of Bit Lines", by Schuster.
K. Hardee et al., "A 30ns 64K CMOS RAM", 1984 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 216-217.

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