Bit line and cell plate clamp circuit for a DRAM

Details Bit line and cell plate clamp circuit for a DRAM Bit line and cell plate clamp circuit for a DRAM

1991-09-05

1993-10-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including signal clamping

36518909, 365149, 365203, G11C 700

Patent

active

052532054

ABSTRACT:
A supply circuit providing an intermediate voltage between Vss and Vcc for a DRAM is coupled to both the cell capacitor plates and the bit line clamp transistors. The supply circuit includes a logic circuit which ANDs the equilibration signal and a restore complete signal thereby to provide a timing signal in the initial portion of the precharge epoch. The timing signal turns on first and second transistors which operate as a load to develop a voltage at first and second nodes. The voltage so developed is a transition voltage above the target holding voltage. This voltage is stored on a storage capacitor, and to the gate electrode of a drive transistor and a third transistor. The drive transistor selectively couples operating voltage to the hold line. After the logic circuit turns off, the offset voltage which has been stored on the capacitor controls the drive transistor to couple the target holding voltage to the holding line.

REFERENCES:
patent: 4491936 (1985-01-01), Eaton, Jr. et al.
patent: 4799193 (1989-01-01), Horiguchi et al.
patent: 4965769 (1990-10-01), Etoh et al.

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