Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
1999-12-30
2003-05-13
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
Reexamination Certificate
active
06564343
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
In general, The present invention relates to a bit interleave circuit and a bit deinterleave circuit which are used in a mobile communication system or a mobile broadcasting system.
2. Description of the Related Art
In a system where information is communicated or broadcasted by using a radio wave to a movable body such as an automobile, there is a problem of deterioration in quality of communication due to attenuation of received power which is caused by shadowing or fading. Shadowing is a phenomenon in which an electric wave is blocked by a building or the like. On the other hand, fading is a phenomenon in which interference between multipath delayed waves occurs. In particular, when an FEC (Forward Error Correction) apparatus is used for improving the quality of communication, the ability to correct an error deteriorates in case a burst error is generated by shadowing or fading, raising a problem of a substantially deteriorating quality of communication.
In order to prevent the quality of communication from considerably deteriorating due to shadowing or fading, a bit interleave circuit and a bit deinterleave circuit are employed on the transmitter and receiver sides, respectively in many cases. To put in detail, a random-access memory with a 2-plane configuration is employed so as to allow a series of output codes generated by an error correction encoder to be transmitted by changing the order of the codes in accordance with a proper rule. On the receiver side, on the other hand, the received codes are rearranged in the reverse order to reproduce the original series of codes which is then supplied to an error correction decoder. In this way, burst errors generated along the radio transmission path can be randomized so that the deterioration of the ability to correct an error is reduced.
FIG. 22
is a diagram showing the configuration of the conventional bit interleave circuit and
FIG. 23
is a diagram showing the configuration of the conventional bit deinterleave circuit.
FIG. 24
is an explanatory diagram used for describing the operations of the bit interleave and bit deinterleave circuits shown in
FIGS. 22 and 23
respectively for an interleave block of 4×4 bits.
(a) Bit Interleave Operation
As shown in
FIG. 24
, information coded by an FEC encoder
50
by adopting a convolution encoding technique or the like is converted into serial data by a P/S converter
52
before being fed to the bit interleave circuit
54
shown in FIG.
22
. In the bit interleave circuit
54
, a horizontal-direction counter
6
employed in a write-address counter
2
counts the number of clocks synchronized with an input signal repeatedly from
0
to
3
, outputting the clock count to an address terminal of either a RAM
16
#
0
or a RAM
16
#
1
by way of a selector
14
#
0
or
14
#
1
, respectively as a lower-order address.
On the other hand, a vertical-direction counter
4
also employed in the write-address counter
2
counts the number of clock periods repeatedly from
0
to
3
, outputting the clock-period count to the address terminal of either the RAM
16
#
0
or the RAM
16
#
1
by way of the selector
14
#
0
or
14
#
1
, respectively as an upper-order address. By a clock period, the counting period of the horizontal-direction counter
6
is meant. A RAM plane switching control signal controls the RAMs
16
#
0
and
16
#
1
so that their write-in and read-out operations are mutually exclusive. To be more specific, when a read operation is carried out on one of the RAMs
16
#
0
or
16
#
1
, a write operation is carried out on the other.
A gate circuit
18
#
0
supplies a RAM write timing signal to a write enable terminal WE of the RAM
16
#
0
in accordance with the RAM plane switching control signal. By the same token, a gate circuit
18
#
1
supplies a RAM write timing signal to a write enable terminal WE of the RAM
16
#
1
in accordance with the RAM plane switching control signal. A gate circuit
20
#
0
receives a serial transmission signal (0 to F), outputting the signal to a terminal data #
0
of the RAM
16
#
0
in accordance with the RAM plane switching control signal. By the same token, a gate circuit
20
#
1
receives a serial transmission signal (0 to F), outputting the signal to a terminal data #
0
of the RAM
16
#
1
in accordance with the RAM plane switching control signal. It should be noted that the reference numerals 0 to F are hexadecimal numbers representing the contents of the encoded list.
When the RAM write timing signal supplied to the write enable terminal WE of the RAM
16
#
0
or
16
#
1
is active, the encoded list supplied to the terminal data #
0
is written into a location in the RAM
16
#
0
or
16
#
1
indicated by the address signal supplied to the address terminal. As a result, the contents of the i-th encoded list are written into a location at the address i as shown in
FIG. 24. A
vertical-direction counter
12
employed in a read-address counter
8
repeatedly counts the number of clocks synchronized with an input signal from
0
to
3
, outputting the clock count to the selector either
14
#
0
or
14
#
1
, respectively as an upper-order address.
On the other hand, a horizontal-direction counter
10
also employed in the read-address counter
8
counts the number of clock periods repeatedly from
0
to
3
, outputting the clock-period count to the address terminal of either the RAM
16
#
0
or the RAM
16
#
1
by way of the selector
14
#
0
or
14
#
1
, respectively as a lower-order address. By a clock period, the counting period of the vertical-direction counter
12
is meant. Either of the RAMs
16
#
0
and the
16
#
1
outputs an encoded list from a location indicated by an address supplied to the address terminal thereof to a transmission system by way of a selector
22
. In this way, the signal to be transmitted is interleaved in the order of
0
,
4
,
8
, C,
1
,
5
,
9
and so on.
(b) Bit Deinterleave Operation
In the bit deinterleave circuit
56
shown in
FIG. 23
, a vertical-direction counter
34
employed in a write-address counter
30
counts the number of clocks synchronized with an input signal, repeatedly from
0
to
3
, outputting the clock count to the address terminal of either a RAM
42
#
0
or a RAM
42
#
1
by way of a selector
40
#
0
or
40
#
1
, respectively as an upper-order address. On the other hand, a horizontal-direction counter
32
also employed in the write-address counter
30
counts the number of clock periods repeatedly from
0
to
3
, outputting the clock-period count to the address terminal of either the RAM
42
#
0
or the RAM
42
#
1
by way of the selector
40
#
0
or
40
#
1
, respectively as a lower-order address. By a clock period, the counting period of the vertical-direction counter
34
is meant. Data supplied to the terminal data #
0
is written into a location in the RAM
42
#
0
or
42
#
1
indicated by the address signal supplied to the address terminal. As a result, a signal i received in the order of
0
,
4
,
8
, C,
1
and so on is written at an address i where i is the order number of the encoded list prior to the interleave process.
A horizontal-direction counter
39
employed in a read-address counter
36
repeatedly counts the number of clocks synchronized with an input signal from
0
to
3
, outputting the clock count to the address terminal of either the RAM
42
#
0
or the RAM
42
#
1
by way of the selector
40
#
0
or
40
#
1
, respectively as a lower-order address. On the other hand, a vertical-direction counter
38
also employed in the read-address counter
36
counts the number of clock periods repeatedly from
0
to
3
, outputting the clock-period count to the address terminal of either the RAM
42
#
0
or the RAM
42
#
1
by way of the selector
40
#
0
or
40
#
1
, respectively as an upper-or
Chase Shelly A
De'cady Albert
Fujitsu Limited
LandOfFree
Bit interleave circuit and bit deinterleave circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bit interleave circuit and bit deinterleave circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bit interleave circuit and bit deinterleave circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3027150