Bit clock regeneration circuit for PCM data, implementable on in

Details Bit clock regeneration circuit for PCM data, implementable on in Bit clock regeneration circuit for PCM data, implementable on in

1994-05-17

1995-11-28

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375214, 375215, 375373, H03D 324, H03K 1100

Patent

active

054715024

ABSTRACT:
In a bit clock generation circuitry, a T/2 pulse generator includes a monostable multivibrator triggered by an edge of an input PCM data signal and controlled by a time constant adjusting signal so as to generate a pulse signal having its pulse width adjusted in accordance with the time constant adjusting signal. In response to a pulse signal generated by the monostable multivibrator, a D-type flipflop latches the input PCM data signal for generating a delayed data signal delayed from the input PCM data signal by T/2. An exclusive-OR means receives the input PCM data signal and the delayed data signal for generating a T/2 pulse signal.

REFERENCES:
patent: 4752942 (1988-06-01), Iwakami
patent: 4984255 (1991-01-01), Davis et al.
patent: 5208839 (1993-05-01), Hladik et al.

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