Bist jitter tolerance measurement technique

Details Bist jitter tolerance measurement technique Bist jitter tolerance measurement technique

1995-10-16

1998-08-11

Vo, Don N.

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375376, 375226, 455 674, H04L 700

Patent

active

057938229

ABSTRACT:
A circuit in a semiconductor device for testing jitter tolerance of a receiver in the semiconductor device. The circuit includes a jitter injection circuit that has an output connected to an input in a phase-locked loop circuit. The jitter injection circuit generates an output signal in response to an application of an input signal. The phase-locked loop circuit has an output that generates a clock signal, wherein the clock signal may be altered by the output signal from the jitter injection circuit. The clock signal from the phase-locked loop circuit controls transmission of data at the transmitter. Alteration of the clock signal caused by the jitter injection circuit alters the manner in which the transmitter transmits data.

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patent: 5309428 (1994-05-01), Copley et al.
patent: 5515404 (1996-05-01), Pearce

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