Bist architecture for measurement of integrated circuit delays

Details Bist architecture for measurement of integrated circuit delays Bist architecture for measurement of integrated circuit delays

1996-12-20

1999-07-13

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

059236760

ABSTRACT:
A built-in self-test (BIST) method and apparatus for digital integrated circuits (ICs) and for systems including multiple ICs, measures signal propagation delays in combinational and sequential logic, set-up and hold times, and tri-state enable/disable times, from any circuit node to any other circuit node including pin-to-pin and from one IC to another. The IC under test is provided with two test bus conductors passing near every circuit node of interest and connected thereto by switches or buffers. During test, an oscillator is created including the test bus, a constant delay, counters, and a delay path of interest or a reference path. The delay path of interest may include e.g. an analog filter. The oscillation period of the oscillator when the reference path is selected is subtracted from the oscillation period when the oscillator includes a delay path of interest. A circuit automatically accommodates inverting and non-inverting paths. A delay copier copies the delay between any two signal events, without injecting any test signal into the circuit under test (e.g. on-line test), and the delay copy can be measured by selecting it in the oscillator.

REFERENCES:
patent: 5083299 (1992-01-01), Schwanke et al.
patent: 5132685 (1992-07-01), DeWitt et al.
patent: 5822267 (1998-10-01), Watanabe et al.
Marcelo Lubaszewski et al., "A Multifunctional Test Structure for Analog BIST", International Mixed Signal Testing Workshop Proceedings, May 1996, pp. 239-244.

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