Bipolar transistors with isolation trenches to reduce...

Details Bipolar transistors with isolation trenches to reduce... Bipolar transistors with isolation trenches to reduce...

1999-08-10

2001-04-17

Lee, Eddie C. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

Plural non-isolated transistor structures in same structure

C257S575000, C257S588000, C257S564000, C257S505000

Reexamination Certificate

active

06218725

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to fabrication of a bipolar transistor, and more particularly to the bipolar transistor and a method for fabricating the same adapted to reduce chip size and production costs.
BACKGROUND OF THE INVENTION
FIG. 1
is a cross-sectional view of a conventional bipolar transistor structure.
Referring to
FIG. 1
, in a conventional bipolar transistor of SBC (Standard Buried Collector) structure, an epitaxial layer (
6
) is formed on a p
−
-type semiconductor substrate (
2
). A n
+
-type buried layer (
4
) is formed between the semiconductor substrate (
2
) and the epitaxial layer (
6
), and a p
+
-type isolation region (
8
) is formed at both sides of the n
+
-type buried layer (
4
). An n
+
-type sink layer (
10
) is formed to be in contact with the upper part of epitaxial layer (
6
) and the buried layer (
4
). A p-type base region (
12
) is formed in the epitaxial layer (
6
) between the isolation regions (
8
), and an n
+
-type emitter region (
14
) is formed in the p-type base region (
12
). An emitter electrode (
18
), a base electrode (
19
), and a collector electrode (
20
) are formed through an insulating layer (
16
) for respective electrical connection with the emitter (
14
) , the base region (
12
), and the sink layer (
10
), wherein the insulating layer (
16
) is formed on the epitaxial layer (
6
). As described above the SBC structure bipolar transistor reduces the collector resistance by forming the buried layer (
4
), and increases internal pressure by forming the lightly doped epitaxial layer (
6
) so that the bipolar transistor is a more ideal device. However, there are problems in that the production cost is increased by forming the epitaxial layer (
6
) and the chip size is increasing by forming the isolation region (
8
) separately. Also, it is difficult to reduce the chip size because of diffusion of the sink layer (
10
), wherein the diffusion occurs by a following annealing.
FIG. 2
is a cross-sectional view of another conventional bipolar transistor structure.
As shown in
FIG. 2
, in another conventional bipolar transistor of triple diffusion structure, an n-type collector region (
24
) is formed in a p
−
-type semiconductor substrate (
22
) and a p-type base region (
26
) is formed in the collector region (
24
). An n
+
-type emitter region (
28
a
) is formed in the base region (
26
), and a n
+
-type collector contact region (
28
b
) is formed in the collector region (
24
) of the outer portion of the extrinsic base region (
26
). An emitter electrode (
32
), a base electrode (
33
), and a collector electrode (
34
) are formed in order to respectively electrically connect with the emitter region (
28
a
), the base region (
26
), and the collector contact region (
28
b
) through the insulating layer, wherein the insulating layer is formed on the semiconductor substrate (
22
). As described above, there are advantages in that the production cost is relatively cheap and the chip size is relatively small because the bipolar transistor having a triple diffusion structure does not require formation of the epitaxial layer and an additional isolation region. However, the bipolar transistor has several problems, as follows. Increasing the quantity of the injecting ions, in order to reduce the collector resistance, makes the formation of the base region (
26
) and emitter region (
28
a
) difficult, and the internal pressure is decreased. On the other hand, as the quantity of the injecting ions is decreased, the resistance of collector is increased.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a bipolar transistor having good characteristics without the formation of an epitaxial layer as well as an isolation region, and to provide a method for fabricating the same.
It is another object of the present invention to provide a bipolar transistor which can be reduced in chip size and production cost, and to provide a method for fabricating the same.
According to an aspect of the present invention, a method of fabricating a bipolar transistor comprises the steps of: forming a well region in a semiconductor substrate of first conductivity type, the well region having a second conductivity type; etching the semiconductor substrate to form a trench at both sides of the well region; forming a first insulating layer on both sidewalls of the trench; injecting an impurity of the second conductivity type into a bottom of the trench to form a buried layer of the second conductivity type at the bottom thereof; filling up the trench with a conductive layer so as to electrically connect the conductive layer to the buried layer; forming a second insulating layer over the semiconductor substrate; injecting an impurity of the first conductivity type into the semiconductor substrate using a masking layer whose pattern covers a central portion of the well region to form an extrinsic base region; forming a device isolation region on the semiconductor substrate using the masking layer; removing the masking layer; injecting an impurity of the first conductivity type using the device isolation region as a mask to form an intrinsic base region; and injecting an impurity of the second conductivity type using the device isolation region as a mask to form an emitter region in the intrinsic base region.
According to another aspect of the present invention, a bipolar transistor comprises a semiconductor substrate of first conductivity type; a well region of second conductivity type formed in the semiconductor substrate; an isolation trench formed in the semiconductor substrate and at both ends of the well regions, the isolation trench having an insulating layer formed on both sidewalls of the trench and a conductive layer filled in the trench; a buried layer of the second conductivity type formed of two regions surrounding respective bottom portions of two adjacent isolation trenches and being in direct contact with the well region, these two regions being electrically connected with each other; two extrinsic base regions formed at respective sides of the two adjacent isolation trenches and in the well region; an intrinsic base region formed between the two extrinsic base regions and in the well region; and an emitter region formed on the intrinsic base region.


REFERENCES:
patent: 4980304 (1990-12-01), Chin et al.
patent: 5397912 (1995-03-01), Sundaram
patent: 5506157 (1996-04-01), Lee et al.
patent: 5614750 (1997-03-01), Ellul et al.

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