Bipolar transistor with reduced parasitic capacitance

Details Bipolar transistor with reduced parasitic capacitance Bipolar transistor with reduced parasitic capacitance

1988-03-30

1991-01-08

Larkins, William D.

357 20, 357 34, 357 52, 357 59, H01L 27082, H01L 23535

Patent

active

049840533

ABSTRACT:
A bipolar integrated circuit having a polysilicon contact (26) to a heavily doped graft base region 24g which is spaced from oxide isolation walls 22 by a distance sufficiently small that in operation, the surface portion 37 of the collector region 23 is fully depleted from the graft base region 24g to the oxide isolation 22, so that base-collector capacitance is reduced due to the graft base being smaller than the oxide isolated island and by the absence of capacitance between the sides of the graft base region and the collector, while capacitance between the polysilicon contact 26 and the collector is also decreased by the depleted surface portion 37 of the collector.

REFERENCES:
patent: Re27045 (1971-02-01), Yu
patent: 4003072 (1977-01-01), Matsushita et al.
patent: 4153904 (1979-05-01), Tasich, Jr. et al.
patent: 4292642 (1981-09-01), Appels et al.
patent: 4562451 (1985-12-01), Fuse
patent: 4642674 (1987-02-01), Schoofs
patent: 4729965 (1988-03-01), Tamaki et al.
patent: 4731341 (1988-03-01), Kawakatsu
patent: 4803541 (1989-02-01), Kouda
patent: 4868624 (1989-09-01), Grung et al.

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