Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-29
2003-12-23
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06667521
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to bipolar transistors and, more particularly, to a process for forming a bipolar transistor with a raised extrinsic base in an integrated bipolar and complementary metal-oxide-semiconductor (BiCMOS) transistor circuit.
BACKGROUND OF THE INVENTION
Transistors are used as either amplifying or switching devices in electronic circuits. In the first application, the transistor functions to amplify small ac signals. In the second application, a small current is used to switch the transistor between an “on” state and an “off” state.
The bipolar transistor is an electronic device with two p-n junctions in close proximity. The bipolar transistor has three device regions: an emitter, a collector, and a base disposed between the emitter and the collector. Ideally, the two p-n junctions (the emitter-base and collector-base junctions) are in a single layer of semiconductor material separated by a specific distance. Modulation of the current flow in one p-n junction by changing the bias of the nearby junction is called “bipolar-transistor action.”
External leads can be attached to each of the three regions and external voltages and currents can be applied to the device using these leads. If the emitter and collector are doped n-type and the base is doped p-type, the device is an “npn” transistor. Alternatively, if the opposite doping configuration is used, the device is a “pnp” transistor. Because the mobility of minority carriers (i.e., electrons) in the base region of npn transistors is higher than that of holes in the base of pnp transistors, higher-frequency operation and higher-speed performances can be obtained with npn devices. Therefore, npn transistors comprise the majority of bipolar transistors used to build integrated circuits.
As the vertical dimensions of the bipolar transistor are scaled more and more, serious device operational limitations have been encountered. One actively studied approach to overcome these limitations is to build transistors with emitter materials whose band gaps are larger than the band gaps of the material used in the base. Such structures are called heterojunction transistors.
Heterostructures comprising heterojunctions can be used for both majority carrier and minority carrier devices. Among majority carrier devices, heterojunction bipolar transistors (HBTs) in which the emitter is formed of silicon (Si) and the base of a silicon-germanium (SiGe) alloy have recently been developed. The silicon-germanium alloy (often expressed simply as silicon-germanium) is narrower in band gap than silicon.
The advanced silicon-germanium bipolar and complementary metal-oxide-semiconductor (BiCMOS) technology uses a silicon-germanium base in the heterojunction bipolar transistor. In the high frequency (such as multi-GHz) regime, conventional compound semiconductors such as GaAs and InP currently dominate the market for high speed wired and wireless communications. Silicon-germanium BiCMOS promises not only a comparable performance to GaAs in devices such as power amplifiers, but also a substantial cost reduction due to the integration of heterojunction bipolar transistors with standard CMOS, yielding the so-called “system on a chip.”
For high performance HBT fabrication, yielding SiGe/Si HBTs, a conventional way to reduce the base resistance is through ion implantation onto the extrinsic base. The ion implantation will cause damage, however, to the base region. Such damage ultimately may lead to degradation in device performance.
To avoid the implantation damage, a raised extrinsic base (REXT) is formed by depositing an extra layer of polycrystalline silicon (or silicon-germanium) atop the conventional SiGe extrinsic base layer. There are essentially two processes that may be applied to achieve such a raised extrinsic base. The first process involves selective epitaxy; the other involves chemical-mechanical polishing (CMP).
1. Selective Epitaxy
In a typical selective epitaxy process, the raised extrinsic base polycrystalline silicon is formed before the deposition of the intrinsic base SiGe. The intrinsic base SiGe is deposited selectively onto the exposed surface of silicon and polycrystalline silicon inside an over-hanging cavity structure. The selective epitaxy with a cavity structure mandates stringent process requirements for good selectivity, and suffers from poor process control.
U.S. Pat. No. 5,523,606 issued to Yamazaki discloses a process using selective epitaxy. Referring to
FIGS. 1A and 1B
, which correspond to portions of
FIGS. 7C and 7E
, respectively, of the '606 patent, the extrinsic base poly silicon
21
is deposited before the intrinsic base
23
is deposited. Shown in
FIG. 1A
are silicon nitride film
15
, silicon nitride side wall spacers
17
, and semiconductor substrate
1
. The films (not labeled) underneath the extrinsic base poly silicon
21
are etched away to form a cavity (or void)
22
of an over-hanging structure. The intrinsic base
23
is then selectively deposited, as shown in
FIG. 1B
, only inside the cavity
22
on the silicon and polysilicon exposed surface. See '606 patent from column 8, line 53 to column 9, line 17.
FIG. 1B
also shows an n-type epitaxial collector layer
13
. The approach disclosed in the '606 patent avoids a CMP step, but has several drawbacks such as poor process control in filling the cavity
22
and stringent requirements for selective deposition conditions.
U.S. Pat. No. 5,620,908 was issued to Inoh et al. and titled “Manufacturing Method of Semiconductor Device Comprising BICMOS Transistor.” Inoh et al. apply an approach similar to that disclosed by Yamazaki in the '606 patent. Specifically, as illustrated in FIG. 6F of the '908 patent and discussed in column 13 (specifically, at lines 24-26), Inoh et al. disclose a process that incorporates selective epitaxy and the step of etching an overhang to form a cavity.
2. CMP
The second type of process that can be applied to form a raised extrinsic base involves a CMP step. U.S. Pat. No. 5,015,594 was issued to Chu et al. and was assigned to the same assignee, International Business Machines Corporation, as the present invention. In their patent, titled “Process of Making BICMOS Devices Having Closely Spaced Device Regions,” Chu et al. propose the formation of extrinsic base polysilicon by CMP. The isolation is achieved by thermal oxidation, however, which is not feasible in high performance devices due to the high temperature thermal process.
Y. C. Sun and J. Warnock disclose a process, in “Process for a High-Performance Bipolar-Based BICMOS,” IBM Technical Disclosure Bulletin, vol. 35, no. 4B, pages 295-97 (September 1992), of forming a raised extrinsic base by CMP. The extrinsic base portion is formed in direct contact with the intrinsic base, however, without any etch stop.
FIGS. 2A and 2B
correspond to
FIG. 1
of the article. With reference to
FIGS. 2A and 2B
, the extrinsic base polysilicon
21
is deposited directly above the intrinsic base region
5
, which is also on the emitter opening region, without any interfacial films to stop the emitter opening etch
31
of the extrinsic base polysilicon
21
. This process exhibits poor process control and, therefore, cannot yield good production control and cannot yield a highly reliable and reproducible bipolar device.
To stop the extrinsic polysilicon etch during formation of the emitter opening, an etch stop layer of dielectric materials such as oxide must be disposed underneath the extrinsic base polysilicon. This etch stop layer cannot cover the whole extrinsic base region, however, in order to form an electrical contact between the raised extrinsic base and the underneath base
25
. Therefore, a need remains for a feasible approach to achieve those required features with CMOS circuit integration capability.
The deficiencies of the conventional methods show that a need still exists for an improved process of fabricating an HBT with a raised extrinsic base. To overcome the shortcomings of the conventional methods, a n
Ahlgren David C.
Freeman Gregory G.
Huang Feng Yi
Ticknor Adam D.
Abate Joseph P.
Hoang Quoc
Nelms David
Ratner & Prestia
LandOfFree
Bipolar transistor with raised extrinsic base fabricated in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bipolar transistor with raised extrinsic base fabricated in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bipolar transistor with raised extrinsic base fabricated in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3171293