Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2006-05-02
2006-05-02
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S316000, C438S318000, C438S320000, C438S341000, C438S350000, C438S356000, C438S357000, C438S359000
Reexamination Certificate
active
07037798
ABSTRACT:
The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.
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Washio, K. et al., “A Selective-Epitaxial-Growth SiGe-Base HBT With SMI Electrodes Featuring 9.3-ps ECL-Gate Delray,” IEEE Transactions on Electron Devices, vol. 46, No. 7, Jul. 1999, pp. 1411-1416.
Adam Thomas N.
Chan Kevin K.
Joseph Alvin J.
Khater Marwan H.
Liu Qizhi
Cai Yuanmin
Ghyka Alexander
Hoffman Warnick & D'Alessandro LLC
Lee Kyoung
LandOfFree
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