Bipolar transistor memory cell and method

Static information storage and retrieval – Systems using particular element – Flip-flop

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365155, 365156, 365180, 3652256, G11C 1100, G11C 1134

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052894096

ABSTRACT:
Bipolar transistor memory cell and method for use in a random access memory. A pair of state elements are cross coupled so that they assume opposite states in accordance with signals applied thereto, a pair of bipolar pass transistors are connected to respective ones of the state elements for applying signals to the state elements, and current flow through the pass transistors is monitored to determine the states of the state elements.

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IBM Technical Disclosure Bulletin, vol. 33, No. 18, Jun. 1990, pp. 328 and 329, "Dual-Port Bipolar Memory Cell With Soft Error Rate Immunity".
IBM Technical Disclosure Bulletin, vol. 30, No. 9, Feb. 1988, pp. 253 and 254, "Transistor Gated CTS Memory Cell".
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Cavaliere et al., "Bipolar RAM Cell With Bilateral NPN Bitline Coupling Transistors" IBM Tech. Disc. Bull. vol. 20, No. 4, Sep. 1977, pp. 1447-1450.

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