Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2002-02-14
2003-08-12
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S565000
Reexamination Certificate
active
06605825
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the characterization of bipolar transistors, and more particularly to a novel heterojunction bipolar transistor (HBT) test structure and method in which test probe pads are provided lateral to respective transistor regions prior to forming an upper metallization.
2. Description of the Related Art
In characterizing newly manufactured bipolar transistors to determine whether they operate properly and meet specifications, a small portion of the transistors on a wafer (typically less than one percent) are dedicated as test devices. Since all of the transistors on the wafer are fabricated in a common process, they will generally exhibit common operating characteristics. Therefore, characterizing the relatively few test transistors can be taken as a characterization of the larger number of circuit transistors that are employed in the operating circuitry of the wafer.
When the transistor fabrication has been completed, the wafer is coated with one or more dielectric layers, with metallized leads formed on each layer and extending through the underlying dielectric to establish electrical connections with the transistors. The metallization for the test transistors is provided with enlarged probe pads on the upper dielectric surface so that the test transistors can be electrically accessed via test probes brought into contact with the contact pads. (The term “metallization” as used herein is not limited to conventional metal elements, but also encompasses alternate conductive mechanisms such as heavily doped semiconductor.)
While this approach has been found to be effective in characterizing a large number of transistors by actually testing only a small portion, it requires that the wafer fabrication be fully completed before characterization can take place. Thus, if the test transistors do not meet specifications, the completed wafer must be discarded. This is costly in terms of both processing time and expense.
SUMMARY OF THE INVENTION
The present invention seeks to provide a novel test transistor structure and associated characterization method that allows transistor characterization to be completed before the wafer has been fully fabricated, and in particular before the upper metallization is laid down. The invention is particularly applicable to HBTs, and permits bad wafers to be identified and discarded without incurring the cost and time necessary to fabricate the upper metallization.
These goals are achieved according to one embodiment of the invention by providing test probe pads, of sufficient size to receive test probes, lateral to, spaced from and substantially coplanar with one or more of the test transistor emitter, base and collector regions. The probe pads are fabricated prior to forming the upper metallization, and are preferably disposed on pedestals and connected to their associated transistor regions by air bridges. For an HBT, air bridge connections are preferably made to the emitter and base from probe pads on respective pedestals lateral to and spaced from the transistor, while a collector contact is made via the subcollector, either by an air bridge to a probe contact on a separate pedestal, or by a lead which extends along the substrate to a separate probe pad. A gap is preferably provided in the subcollector below the air bridges to reduce capacitive coupling. The test probe pads, air bridges and their respective transistor regions are preferably formed in respective simultaneous common metallizations.
Once the transistors have been fabricated, but prior to forming the upper metallization, the test transistors are accessed and characterized via their respective probe pads. If the transistors do not meet specifications, the wafer can be discarded in its partially completed state. The upper metallization is fabricated only if the test transistors meet specifications, thus characterizing the circuit transistors as operating properly. Connections to the circuit transistors are then made through the dielectric underlying the upper metallization, while the test transistors need not be accessed again.
REFERENCES:
patent: 4079505 (1978-03-01), Hirano et al.
Brar Berinder P. S.
Higgins John A.
Li James Chingwei
Fahmy Wael
Farahani Dana
Innovative Technology Licensing LLC
Koppel, Jacobs Patrick & Heybl
LandOfFree
Bipolar transistor characterization apparatus with lateral... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bipolar transistor characterization apparatus with lateral..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bipolar transistor characterization apparatus with lateral... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3098280