Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Mesa or stacked emitter
Reexamination Certificate
2002-06-28
2004-10-12
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Mesa or stacked emitter
Reexamination Certificate
active
06803289
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method for fabricating a bipolar transistor.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
In general, bipolar transistors offer relatively fast switching speeds and therefore, are often used in integrated circuit design. However, the fabrication of bipolar transistors typically requires several steps, thereby increasing the complexity of the fabrication process of the integrated circuit. For example, a bipolar transistor is generally fabricated by forming an epitaxial layer upon a semiconductor topography followed by the deposition of silicon dioxide and, in some embodiments, the deposition of silicon nitride. Consequently, a conductive layer formed above the dielectric layer/s may be patterned such that a conductive structure of the transistor may be formed dielectrically spaced above the epitaxial layer. In particular, the fabrication process may include patterning the dielectric and conductive layers to form the structures of the transistor. As such, the fabrication process of a bipolar transistor may further include formation of resist pattern masks and etching processes.
As stated above, silicon nitride may be used to during the fabrication of a bipolar transistor. Such a material may serve as an etch stop during the patterning of the overlying conductive layer. In some cases, the silicon nitride layer may serve to closely control the formation of the opening formed through the dielectric layers to the underlying epitaxial layer by first etching the nitride layer and then etching the silicon dioxide layer. In order to reduce the thermal budget of the fabrication process, however, the deposition of the nitride layer is often limited to a low-temperature process, specifically at temperatures less than approximately 400° C. One manner with which to deposit at such a low temperature is to use a plasma enhanced chemical vapor deposition (PECVD) process. However, nitride deposited using a PECVD process at relatively low temperatures is undesirably porous and easily deteriorates upon exposure to relatively dilute etch chemistries. Consequently, control of etching the nitride layer without substantially etching portions of underlying layers is difficult. In addition, a low-temperature deposited PECVD nitride layer may not adequately serve as an etch stop layer since the layer will be more susceptible to being etched at a faster rate than a high-temperature deposited nitride layer.
In addition, nitride is not typically deposited in uniform conformal manner using a low-temperature PECVD deposition process. In particular, PECVD nitride deposited at low temperatures typically deposits more material along horizontal surfaces of an underlying topography than along vertical surfaces of an underlying topography. For example, in some cases, low-temperature PECVD nitride deposited along a vertical surface of an underlying topography may include a thickness that is approximately 40% of the thickness of the PECVD nitride layer arranged along a horizontal surface of the underlying topography. As such, regions of the underlying topography including vertical surfaces may be exposed more quickly during an etch process than regions of the topography including horizontal surfaces. Consequently, the etch process used to remove the PECVD nitride layer may undesirably etch vertical portions of the underlying topography while portions of the PECVD nitride layer upon the horizontal surfaces of the underlying topography are being removed. The etching of such portions of the underlying topography may undesirably remove portions of device structures, affecting the functionality of the device.
In some cases, bipolar transistors may be fabricated adjacent to CMOS transistors to form a transistor commonly referred to as a “BiCMOS transistor.” In such an embodiment, the gate structures of the CMOS transistors are typically formed prior to the bipolar transistors and therefore, the nitride layer may be deposited above the gate structures of the CMOS devices. In cases in which less nitride is deposited on the sidewalls of the gate structures than adjacent horizontal surfaces, the gate structures may be undesirably etched during the removal of the nitride layer. In addition, BiCMOS transistors may be susceptible to a larger accumulation of nitride material in between the transistors due to the large aspect ratio of spacings between the transistors and the nonconformal deposition characteristics of PECVD silicon nitride. Consequently, the etch process of the nitride layer may need to be extended in order to remove the entire nitride layer, particularly in between the transistors. Such an extension of the etch process may further deteriorate the gate structures and other structures arranged laterally adjacent to the transistors.
Therefore, it would be advantageous to develop a method for fabricating a bipolar transistor that overcomes one or all of the aforementioned problems. In particular, it would be beneficial to develop a method for fabricating bipolar transistor in less processing steps than the conventional method. In addition, it would be advantageous to develop an improved method for controlling the removal of exposed portions of dielectric layers within a bipolar transistor fabrication process. In particular, it would be beneficial to develop a bipolar fabrication process which does not damage structures within the topography of the transistor during the removal of dielectric layers.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by an improved method for fabricating a bipolar transistor. In particular, the aforementioned problems may be addressed by using different materials and/or process sequences than those used in conventional methods to fabricate a bipolar transistor. For example, in some cases, a method for fabricating a bipolar transistor as described herein may include patterning an epitaxial layer to expose one or more regions of a semiconductor topography prior to the deposition of an intermediate layer upon the exposed regions of the semiconductor topography and remaining portions of the epitaxial layer. In other cases, the intermediate layer may be deposited upon an unpatterned epitaxial layer. In such an embodiment, the epitaxial layer may be subsequently patterned to expose one or more regions of the semiconductor topography.
In some embodiments, the one or more exposed regions of semiconductor topography may include one or more transistors formed within the semiconductor topography. In such a case, the method may include conformally depositing the intermediate layer above and about the one or more transistors such that the thickness of the intermediate layer is substantially uniform along peripheries of the one or more transistors and in spacings between the one or more transistors. Such a conformal deposition of the intermediate layer may generate a thickness variation of less than approximately 20%, for example, across the semiconductor topography. An intermediate layer, in such an embodiment, may include amorphous silicon, polysilicon, LPCVD (low pressure chemical vapor deposition) nitride, or any other material that includes such uniform deposition characteristics. In such an embodiment, the intermediate layer may be doped or substantially undoped. In other embodiments, the method may include depositing the intermediate layer above and about the one or more transistors in a non-conformal manner such that the thickness of the intermediate layer is substantially non-uniform along peripheries of the one or more transistors and in spacings between the one or more transistors. The intermediate layer, in such an embodiment, may include silicon nitride, for example, or any other material that includes such non-uniform deposition characteristics.
In some cases, the method may additionally include exposing the intermediate layer to a r
Gopalan Prabhuram
Gorla Chandrasekhar R.
Ratnakumar K. Nirmal
Conley & Rose, P.C.
Cypress Semiconductor Corp.
Daffer Kevin L.
Dolan Jennifer M
Jr. Carl Whitehead
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