Static information storage and retrieval – Read/write circuit – Accelerating charge or discharge
Patent
1993-01-15
1994-03-29
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Accelerating charge or discharge
365177, 36523006, G11C 1140
Patent
active
052991679
ABSTRACT:
A bipolar RAM apparatus comprises a memory cell array where a plurality of memory cells are connected in parallel between a pair of word lines arranged in N rows decoders are provided for the individual rows of the memory cell array respectively and each serves to select the corresponding row of the memory cells. N drive transistors are for driving, when turned on, the rows of the memory cells individually in response to the respective drive outputs of the decoders. N discharge circuits comprise discharge transistors whose emitters are mutually connected in common between the circuits and whose collectors are connected respectively to the word lines in the individual rows. Coupling capacitors apply the inverted signals of the drive outputs at a nonselected time to the bases of the discharge transistors and resistors apply a fixed bias voltage to the bases of the discharge transistors. A constant current source is connected between the emitter common node of the discharge transistors and a reference potential point. There occurs no noise margin reduction, and the necessity of widening the word line is eliminated. Fast transition to a nonselected state is achievable, and the power consumption can be minimized.
REFERENCES:
patent: 4156941 (1979-05-01), Homma et al.
patent: 4366558 (1982-12-01), Homma et al.
patent: 4393476 (1983-07-01), Ong
patent: 4611303 (1986-09-01), Kitano
patent: 4618944 (1986-10-01), Okajima
patent: 4821234 (1989-04-01), Nakase
IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983, A High Speed 16 kbit ECL RAM.
Dinh Son
Kananen Ronald P.
LaRoche Eugene R.
Sony Corporation
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