Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-22
2004-04-20
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S133000, C257S146000, C257S343000, C257S370000
Reexamination Certificate
active
06724043
ABSTRACT:
CLAIM OF PRIORITY
This application is a national phase application under 35 U.S.C. § 371 of International Application No. PCT/GB00/03443, filed Sep. 7, 2000, which was published Mar. 15, 2001, as International Publication No. WO 01/18876.
This invention is generally concerned with the family of power semiconductor devices of the kind which combine bipolar and MOS technology.
There is a wide range of such devices. At one extreme, outside the family, are power MOSFET devices. They included the DMOS power MOSFET fabricated with the vertical DMOS process (DMOS is a double-diffused MOS process). In that process, a device is made on a body of monocrystalline silicon using numerous source/gate cells formed at one surface of the body and coating with a common drain region formed at the opposite surface. The source/gate cells are connected in parallel and provide numerous parallel filaments for current to flow through the main internal region of the device known as the drift region.
The combination of bipolar and MOSFET technology has a bipolar transistor structure to provide the main load current-carrying path through the device and a MOS structure which controls the bipolar transistor. The MOS structure provides a high impedance input consuming little input power. It may thus be made compatible with external control circuitry based on MOS technology.
The bipolar transistor may vary in different devices from an essentially three-layer structure, e.g. an NPN transistor, in which the emitter is closely associated with the source of the MOS part of the device, to structures of four or five layers, for example having a thyristor (e.g., a MOS controlled thyristor, in which the cathode is closely associated with the source of the MOS structure. It is known to implement these different bipolar transistor/MOS devices in a vertical structure in a body of monocrystalline silicon in which the emitter/source or cathode/source/gate is provided as numerous cells at one surface of the body while the collector or anode is provided in common region formed at the opposite surface of the body. For ease of nomenclature, the emitter/source and cathode/source structures may both be generally referred to as “cathode/source” or cathode structure, and the collector and anode may be generally referred to as “anode”. However, it should be noted that the inventive concepts described herein can be applied to devices in which N type materials are replaced with P type materials and vice versa.
In operation, the cathode/source/gate cells in a device are connected in parallel, which may be done by internal device metallisation. It is a common feature of the family of devices that the current path to the anode from the cathode structure lies through a drift region. In designing such devices, there is a balance to be achieved between a low resistance forward conduction path and a high forward breakdown voltage capability.
One device of the power bipolar/MOSFET semiconductor family which has gained wide application is the insulated gate bipolar transistor (IGBT) which is an PNP transistor controlled by an N channel enhancement-type MOSFET. The IGBT is a three-terminal device. A second device is the emitter-switched thyristor (EST) which has two integrated MOSFETs with their gates connected to a common gate terminal. It is likewise a three-terminal device. A third device is a four-terminal device of the thyristor type having a separate gate turn-off facility in addition to the usual control gate for turning the device on.
The cathode cell structure of MOSFETs and of bipolar/MOS devices may be fabricated in a planar gate structure at the semiconductor surface or utilising trench gates first developed in connection with power MOSFETs. The cathode structures may also be implemented in planar or trench form.
The cathode structure for IGBTs is discussed in “Analysis of Device Structures for Next Generation IGBT”, Y. Onishi et al, Proceedings of 1998 International Symposium on Power Semiconductor Devices and ICs, p. 85. The paper discusses the structure as applied in both planar gate and trench gate and the relative merits and deficiencies of the two. In the devices the channels of a respective pair of adjacent cells are formed in a common P well.
An insulated-gate controlled thyristor is disclosed in “A Filamentation—Free Insulated-Gate Controlled Thyristor and Comparisons to the IGBT”, K. Lilja and W. Fichtner, Proc. ISPSD, p. 275, 1996. This proposes a device (IGCT) to improve reliability in terms of filamentation failures while preserving thyristor-like on-state properties.
Another form of four-terminal MOS-gated thyristor switch having a gate turn-off facility, referred to as a “FiBS”, is disclosed in “The FiBS, A New High Voltage BiMOS Switch”, K. Lilja, Proc. ISPSD, 1992, p.261, and in U.S. Pat. No. 5,286,981, Lilja et al. A large FiBS would consist of a number of integrated parallel cells. This device can be implemented in planar or trench gate technology.
A MOS-gated Emitter Switched Thyristor is described in “Trench Gate Emitter Switched Thyristors” by M. S. Shekar, J. Korec and B. J. Baliga, Proc. 6th International Symposium of Power Semiconductor Devices and ICs, 1994, paper 5.1, 189. This device is a three-terminal device which is implemented in a trench gate cell structure.
In the prior proposals neighbouring cells can have corresponding structural elements formed within a common doped region or well.
The present invention provides a new form of cathode structure involving clusters of cathode/gate elements. This new form of cluster cathode structure may in turn be used as a cell in a cellular structure form of cathode.
The invention may be implemented in various forms described below. The devices to be described incorporate a MOS-thyristor structure and achieve an enhanced performance while maintaining the desirable characteristics of uniform current distribution, good current saturation performance, small device size (incorporating closely packed cells) and good safe operating area (SOA).
According to the invention there is provided a semiconductor device comprising:
at least one cell comprising a base region of a first conductivity type having disposed therein at least one emitter region of a second conductivity type;
a first well region of a second conductivity type;
a second well region of a first conductivity type;
a drift region of a second conductivity type;
a collector region of a first conductivity type;
a collector contact;
in which each cell is disposed within the first well region and the first well region is disposed within the second well region; the device further comprising:
a first gate disposed over a base region so that a MOSFET channel can be formed between an emitter region and the first well region;
a second gate disposed over the second well region so that a MOSFET channel can be formed between the first well region and the drift region;
and in which the device is configured such that during operation of the device a depletion region at a junction between the base region and the first well region can extend to a junction between the first well region and the second well region, thereby substantially isolating the potential of the first well region from any increase in the potential of the collector contact so that the device can be turned off without having to form a MOSFET channel between the base region and the second well region.
The ability to protect the first well region from excess potentials due to the extension of the depletion region at the junction between the base region and the first well region to the junction between the first well region and the second well region is hereinafter termed “self-clamping”. The self-clamping leads to numerous advantageous features, both in the on-state and off-state of the device, which are discussed in more detail below. Key characteristics of devices of the present invention include: low forward drop; good SOA; high breakdown voltage; switching capabilities which are comparable to those of an IGBT; N-channel MOS gate control; the provision of
Darby & Darby
De Montfort University
Erdem Fazli
Flynn Nathan J.
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