Bipolar memory cell array biasing technique with forward active

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365179, 365190, 3652256, G11C 1140

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active

051173913

ABSTRACT:
A bipolar memory array arranged in a row and column matrix is responsive to a plurality of word line driver transistors for selecting one row of memory cells thereof. The current flowing through each memory cell is provided by a pair or lateral PNP transistor current source loads. The collectors of the word line driver transistors are commonly connected for distributing the source of collector current flowing therethrough between the bases of all of the laterla PNP transistor current sources of the entire memory array which maintains a constant current flow through each of the memory cells during the select and deselect cycles thereby maintaining a constant memory cell array power dissipation which allows for expanded capacity of the memory array and a performance improvement.

REFERENCES:
patent: 4618944 (1986-10-01), Okajima
patent: 4697251 (1985-12-01), Birrittella et al.
patent: 4730277 (1988-03-01), Stipanuk
patent: 4821234 (1989-04-01), Nakase
Wiedmann et al., "Small-Size Low-Power Bipolar Memory Cell", IEEE Journal of Solid-State Circuits vol. SC-6, pp. 355-360.

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