Bipolar memory cell

Details Bipolar memory cell Bipolar memory cell

1984-06-21

1986-04-01

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Flip-flop

365179, 307289, G11C 1140

Patent

active

045802440

ABSTRACT:
A monolithically integrated memory cell having an improved clamped diode load is provided for improving write pulse width and write recovery times. A pair of latchable cross-coupled multi-emitter NPN transistors have a first emitter connected to a stand-by current drain line, and a second emitter coupled to a first bit line and a second bit line, respectively. The base of each transistor is cross-coupled to the collector of the other transistor. The base of each transistor is further coupled to the select line by a PNP transistor. The base of each PNP transistor is coupled to the collector of the respective cross-coupled transistor and is further coupled to the select line by a diode connected NPN transistor. The architecture of the diode connected NPN transistor in the chip prevents substantial stored charge buildup in the epi layer resulting in a lower voltage margin than previously known PN diode or PNP transistor loaded cells, and a higher voltage margin than the previously known Schottky diode loaded cell without the disturb sensitivity.

REFERENCES:
patent: 4311925 (1982-01-01), Chang et al.

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