Bipolar junction transistors having base electrode extensions

Details Bipolar junction transistors having base electrode extensions Bipolar junction transistors having base electrode extensions

2000-02-10

2001-07-03

Dang, Trung (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

With specified electrode means

C257S588000, C257S592000, C438S558000, C438S564000, C438S350000

Reexamination Certificate

active

06255716

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to methods of forming semiconductor devices and devices formed thereby, and more particularly to methods of forming bipolar junction transistors and bipolar junction transistors formed thereby.
BACKGROUND OF THE INVENTION
As state-of-the-art computer systems and circuits evolve, there is a continuing need for higher performance bipolar junction transistors capable of operating at higher switching speeds, with increasing degrees of device integration, and with low rate of failure. There is also a continuing need to shrink or scale down device size to obtain improved device performance.
An attempt to form bipolar junction transistors with reduced lateral dimensions using self-alignment techniques is disclosed in an article by Armin W. Wieder entitled “Submicron Bipolar Technology: New Chances For High Speed Applications”, IEDM, pp. 8-11, (1986). Another attempt to form bipolar junction transistors having self-aligned regions therein is disclosed in U.S. Pat. No. 5,721,147 to Yoon, entitled “Methods of Forming Bipolar Junction Transistors”, the disclosure of which is hereby incorporated herein by reference. Referring now to
FIGS. 1-4
, another conventional method of forming a bipolar junction transistor includes the steps of forming an N-type epitaxial layer
10
(as a collector region) on a P-type substrate (not shown). Field oxide isolation regions
11
may also be formed in the epitaxial layer
10
, using conventional techniques. A first polysilicon layer
12
may be formed on a face of the epitaxial layer
10
and on the isolation regions
11
, as illustrated best by FIG.
1
. This first polysilicon layer
12
may be formed as a P-type layer by implanting P-type impurities into the first polysilicon layer
12
. A first oxide layer
13
is then formed on the first polysilicon layer
12
. Referring now to
FIG. 2
, a masked etching step is then performed to selectively etch through portions of the first oxide layer
13
and first polysilicon layer
12
and expose the N-type epitaxial layer
10
. A second oxide layer
14
may then be deposited on the exposed portion of the N-type epitaxial layer
10
, as illustrated. A relatively highly doped extrinsic base region
15
may then be formed by out-diffusing dopants from the patterned first polysilicon layer
12
into the epitaxial layer
10
. A more lightly doped base link-up region
16
may then be formed by implanting P-type dopants (e.g., B or BF
2
) through the second oxide layer
14
and into the epitaxial layer
10
. The second oxide layer
14
may then be removed.
Referring now to
FIG. 3
, oxide spacers
17
are then formed on the etched sidewalls of the first polysilicon layer
12
and first oxide layer
13
, as illustrated. P-type dopants are again implanted into the epitaxial layer
10
to form an intrinsic base region
18
therein. Here, the oxide spacers
17
and first oxide layer
13
act as an implant mask. Referring now to
FIG. 4
, an N-type emitter contact
19
is then formed on the intrinsic base region. This N-type emitter contact
19
may be formed by depositing an undoped layer of polysilicon, implanting N-type dopants (e.g., arsenic) into the undoped layer of polysilicon and then patterning the layer of polysilicon using conventional techniques. An annealing step may then be performed to cause out-diffusion of N-type dopants from the emitter contact
19
into the intrinsic base region
18
, to define an emitter region
20
therein.
Unfortunately, because it may be difficult to accurately control the thickness of the above-described oxide spacers
17
, it may also be difficult to control important transistor characteristics such as emitter-base junction breakdown voltage (BV
ebo
) current gain &bgr;, unit cutoff frequence f
T
, base resistance, perimeter punch-through voltage, etc. Moreover, because the base link-up region
16
may have a lower P-type doping concentration therein, the formation of thick oxide spacers
17
may cause the base resistance to be unnecessarily large. In addition, the characteristics of the intrinsic base region
18
may not be independently controllable since this region also receives dopants during the step of forming the base link-up region
16
.
Thus, notwithstanding these prior art attempts, there continues to be a need for improved methods of forming bipolar junction transistors.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of forming bipolar junction transistors and transistors formed thereby.
It is another object of the present invention to provide methods of forming bipolar junction transistors having improved electrical characteristics and transistors formed thereby.
It is still a further object of the present invention to provide methods of forming bipolar junction transistors with improved base region characteristics and reduced parasitic capacitance, and transistors formed thereby.
These and other objects, features and advantages of the present invention are provided by methods of forming bipolar junction transistors which include the steps of forming a base electrode of second conductivity type (e.g., P-type) on a face of a substrate. A conductive base electrode extension layer is then formed in contact with a sidewall of the base electrode. The base electrode extension layer may be doped or undoped. An electrically insulating base electrode spacer is then formed on the conductive base electrode extension layer, opposite the sidewall of the base electrode. The conductive base electrode extension layer is then etched to preferably define an L-shaped base electrode extension, using the base electrode spacer as an etching mask. Dopants of second conductivity type are then diffused from the base electrode, through the base electrode extension and into the substrate to define an extrinsic base region therein. This diffusion step can be performed in a controlled manner to limit the extent to which the extrinsic base region dopants adversely affect the electrical characteristics of surrounding regions or contribute to parasitic capacitance. Dopants of second conductivity type are also preferably implanted into the substrate to define an intrinsic base region therein. This dopant implant step is preferably performed using the base electrode spacer as an implant mask. Accordingly, the base electrode spacer is used advantageously as an etching mask and as a dopant implantation mask. An emitter region of first conductivity type is also preferably formed in the intrinsic base region.
According to another embodiment of the present invention, a preferred bipolar junction transistor comprises a substrate containing a collector region of first conductivity type therein and a base region of second conductivity type within the collector region. An emitter region of first conductivity type is also provided within the base region. A base electrode of second conductivity type is provided on a face of the substrate, adjacent the base region. In addition, a preferred base electrode extension of second conductivity type is provided in contact with a sidewall of the base electrode and in contact with the base region at the face. The base electrode extension is preferably formed to have an L-shaped cross-section. An emitter electrode of first conductivity type is provided on the emitter region and in ohmic contact therewith. The base electrode extension and base electrode are separated from the emitter by a base electrode spacer having a first thickness and a base electrode extension spacer having a second thickness which is unequal to the first thickness, respectively. The transistor is also preferably formed so that the base region comprises an extrinsic base region which is self-aligned to the base electrode extension and an intrinsic base region which is self-aligned to the base electrode spacer. The emitter region is also preferably self-aligned to the base electrode extension spacer.


REFERENCES:
patent: 4996581 (1991-02-01), Hamasaki
patent: 5187554 (1993-02-01), Miwa
patent:

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