Bipolar-CMOS static random access memory device with bit line bi

Details Bipolar-CMOS static random access memory device with bit line bi Bipolar-CMOS static random access memory device with bit line bi

1989-03-21

1990-10-02

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36518909, 365177, 365190, 36518906, 365208, G11C 11413

Patent

active

049611682

ABSTRACT:
A bipolar-CMOS static random access memory device includes a plurality of static random access memory cells arranged in columns and rows, complementary pairs of bit lines coupled to the cells in each row, word lines coupled to the cells in each row of the cells and a plurality of sense amplifiers with a separate sense amplifier coupled to each pair of the complementary bit lines. The memory device further includes bipolar pull-up transistors for each of the bit lines, with the collectors of the pull-up transistors coupled to a power supply node and the emitters coupled to the bit lines. Circuitry is provided which biases the bases of the pull-up transistors so that the pull-up transistors are on during a read operation, and so that the pull-up transistor associated with the low side bit line during a write operation is turned off. In addition, the pull-up transistors for both bit lines are biased to the on-state in a write operation for those columns which are not selected.

REFERENCES:
patent: 4539659 (1985-09-01), Dumont
patent: 4616342 (1986-10-01), Miyamoto
patent: 4646268 (1987-02-01), Kuno
patent: 4658159 (1987-04-01), Miyamoto
patent: 4730279 (1988-03-01), Ohtani
patent: 4866674 (1989-09-01), Tran
Ogiue et al., "A 13ns/500 mw 64KB ECL RAM", Digest of Technical Papers, 1986 IEEE Int'l Solid State Circuits Conf. (IEEE, Feb. 20, 1986) pp. 212-213.

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