Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-01
2002-11-05
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S370000, C257S565000
Reexamination Certificate
active
06476452
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device which is useful for the application to a BiCMOS transistor wherein a bipolar transistor and a CMOS transistor are intermixed, and a process for fabricating the same; and in particular to a semiconductor device wherein a bipolar transistor is improved, and a process for fabricating the same.
2. Description of the Prior Art
Recently, it has been demanded to improve the performance of an analogue/digital intermixing LSI (large scale integrated circuit), wherein an analogue circuit and a digital circuit are mounted inside a single chip, and reduce costs thereof with rapid popularization of a personal handy system (PHS), a portable telephone, a communication terminal for a network, and the like.
In general, a CMOS transistor, which can easily make its consumption electric power small, is used as a digital circuit corresponding to high-speed action in the analog/digital intermixing LSI. As an analogue circuit corresponding to high-speed action, a high-performance bipolar transistor is used, and the action of the circuit is performed at a high frequency of several hundreds of MHz to several tens of GHz. Therefore, in order to use the analogue circuit at higher frequencies, it is necessary to improve high frequency characteristics of the bipolar transistor.
As indexes of AC characteristics of the bipolar transistor, fT (cut-off frequency) and fmax (maximum oscillation frequency) are known. Especially, the maximum oscillation frequency fmax, which is an index of driving ability of the bipolar transistor, is a factor for estimating main characteristics of the bipolar transistor. This fmax is approximately represented by the following formula:
f
max≈{square root over ( )}(
fT
/(8
&pgr;·Rb·Ccb
))
wherein Rb represents a base resistance, and Ccb represents a capacity between collector and base (base-to-collector capacitance).
The expression representing the fmax includes fT, as is clearly from the formula 1. Therefore, the fmax shows the total performance of the high frequency characteristics of the bipolar transistor. It can be said that as this value is larger, the high frequency characteristics are better.
Incidentally, it can be understood from this formula 1 that in order to heighten the fmax, it is effective to improve the cut-off frequency fT, and reduce the base resistance Rb and the collector-base capacity.
The following will describe a conventional method for reducing the base resistance Rb and improving the fmax. The conventional technique for reducing the base resistance is described in pages 807 to 810 of 1997 IEDM (International Electron Device Meeting) Technical Digest.
FIG. 1
is a plan view showing an arrangement of respective layers of a conventional bipolar transistor.
FIG. 2
is a sectional view taken along F—F line of FIG.
1
.
FIG. 3
is a sectional view taken along G—G line of FIG.
1
. As shown in
FIGS. 1-3
, in the conventional bipolar transistor a high-concentration N type buried layer
503
is formed on a P type semiconductor substrate
501
. Moreover, an N type epitaxial area
504
is formed to cover the buried layer
503
. In the N type epitaxial area
504
, a pedestal collector
512
, which is an N type area having an impurity concentration that is in the middle of concentrations of the epitaxial area
504
and the buried layer
503
, is formed just under a high-concentration N type diffusion layer
520
, which is an emitter region. In this way, the collector area of the bipolar transistor is composed of the high-concentration N type buried layer
503
, the N type epitaxial area
504
and pedestal collector
512
.
An element separation oxide film
506
is formed in the surface of the N type epitaxial area
504
. This element isolation oxide film
506
is formed to surround an intrinsic base region
509
, a high-concentration P type diffusion layer
518
, and a high-concentration N type diffusion layer
519
. The intrinsic base region
509
and the high-concentration P type diffusion layer
518
are electrically isolated from the high-concentration N type diffusion area
519
by means of the element isolation oxide film
506
. A high-concentration N type diffusion layer
520
is formed inside the intrinsic base region
509
. This high-concentration N type diffusion layer
520
makes an emitter region. An emitter leading-out electrode
513
made of polysilicon is formed to connect this emitter region. A titanium silicide film
521
is formed on the surface of this emitter electrode
513
. The titanium silicide film
521
is also formed on the surface of the high-concentration P type diffusion layer
518
to make an extrinsic base region (a graft base region). The surface of a collector plug region, which is composed of the high-concentration N type diffusion layer
519
, is also covered with the titanium silicide film
521
. An interlayer dielectric
522
is formed on its whole surface. In this interlayer dielectric
522
, base contact holes
524
are made in its extrinsic base region, and a contact hole
525
for collector plug is made in the collector plug region. An emitter contact hole
526
is made in the interlayer dielectric
522
just above the emitter electrode.
The following will describe the form of a plan view arrangement of the above-mentioned conventional bipolar transistor. In this bipolar transistor, the high-concentration P type diffusion layer
518
, the surface of which is covered with the titanium silicide film
521
, is divided into right and left portions in
FIG. 21
by means of the emitter leading-out electrode
513
composed of the second conductive film, the surface of which is covered with the titanium silicide film
521
. The base contact holes
524
are made at right and left positions adjacent to the emitter leading-out electrode
513
composed of the second conductive film, so as to make a form of the arrangement for leading out a non-illustrated metal wiring for leading-out of the base electrode.
The plan view layout according to this method is as follows: the surface of the high-concentration P type diffusion layer
518
is covered with the titanium silicide film having a sheet resistance of about 5 &OHgr;/square and the non-illustrated metal wiring for leading-out of the base electrode is led out at both ends of the emitter leading-out electrode
513
composed of the second conductive film. Therefore, this layout makes it possible to make the base resistance lower than the layout wherein the surface of the high-concentration P type diffusion layer
518
is not covered with any titanium silicide. The above-mentioned known publication states that for this reason the maximum oscillation frequency fmax can be raised up to 54 GHz when the voltage between the collector and the emitter (C-E voltage) is 2.5 V.
The following will describe an example of a process for fabricating the above-mentioned conventional bipolar transistor, referring to
FIGS. 4-10
.
As shown in
FIG. 4
, the high-concentration N type buried layer
503
is formed on the P type semiconductor substrate
501
. The N type epitaxial area
504
of 1 &mgr;m in thickness is formed on the P type semiconductor substrate
501
to cover the high-concentration N type buried layer
503
.
Next, as shown in
FIG. 5
, the element isolation oxide film
506
is formed on the epitaxial area
504
by the LOCOS (Local oxidation of Silicon) method. Furthermore, the first oxide film
505
is formed on the epitaxial area
504
to have a thickness of 12 nm.
Next, as shown in
FIG. 6
, the high-concentration N type diffusion layer
519
is formed, in the portion which becomes the collector plug region between the element isolation oxide films
506
, inside the epitaxial area
504
by ion implantation of, for example, phosphorus. Furthermore, boron is ion-implanted into the epitaxial area
504
at an energy of 7 keV to form the intrinsic base region
509
in the epitaxial area
504
.
Next, as shown in
FIG. 7
, a widow for forming an emitter region is made in the first oxide fi
NEC Corporation
Wilson Allan R.
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