Computer graphics processing and selective visual display system – Computer graphics display memory system – Memory allocation
Reexamination Certificate
2000-08-31
2003-12-02
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Memory allocation
C711S135000, C711S171000
Reexamination Certificate
active
06657635
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to graphics data processing, and in particular to methods and systems for performing binning flush in three-dimensional (3-D) graphics pipelines that use tiled architecture.
Limited memory bandwidth has been a major obstacle in improving the performance of traditional 3-D graphics pipelines. Tiling or “chunking” has evolved as an alternative architecture that reduces the demand on memory bandwidth in 3-D graphics pipelines. A graphics pipeline using tiling architecture segments the rasterization area into a regular grid of tiles. Input geometry and commands are then “binned” into separate memory regions for each tile, such that only the geometry and commands which affect rasterization of a given tile need be read by the rasterization hardware. By storing, for example, one tile worth of data in memory that is local to the processor, main memory bandwidth requirements are significantly reduced. A preferred embodiment for binning of graphics data is described in detail in commonly-assigned patent application Ser. No. 09/271,636, filed Mar. 17, 1999, entitled “Optimized System and Method for Binning of Graphics Data,” by Zhu et al., which is hereby incorporated by reference in its entirety.
Infinite rendering applications where a scene or image may result in unbounded input geometry and commands (e.g. an infinite loop to draw triangles onto the screen) pose a potential problem in this type of graphics data binning. This is so because such infinite rendering images often exhaust the finite amount of memory that is available for such a tiled architecture. The processor must therefore be able to handle these types of images, or other conditions under which binning memory becomes unavailable, without compromising the performance of the graphics pipeline.
SUMMARY OF THE INVENTION
The present invention offers methods and apparatus for flushing binning memory in a 3-D graphics system to address situations where binning memory may become unavailable before binning for a frame has been completed. Broadly, according to the present invention, once it is determined that a binning memory flush must occur (e.g., binning memory is exhausted), geometry and commands binned up to that point are processed (rendered), and the results temporarily stored. As binning memory becomes available again, the necessary intermediate data generated during the partial tile rendering are restored and binning continues. In a specific implementation, the flush is performed on a tile by tile basis. In an alternate implementation, more efficient use of memory is made by flushing directly into other existing memory resources instead of, or in combination with, intermediate buffers.
Accordingly, in one embodiment, the present invention provides a binning flush process that includes generating a flush signal when binning memory becomes unavailable; in response to the flush signal, for each tile, rendering geometry binned and storing the results into intermediate buffers; binning restore commands, the restore commands restoring data generated during partial tile rendering; and continuing with binning input geometry and commands.
In another embodiment, the present invention provides a binning flush process that includes generating a flush signal when binning memory becomes unavailable; in response to the flush signal, selecting preferably the tile which contains the largest amount of binned data; copying the tile descriptor for the selected tile to a special tile descriptor, and marking the original tile descriptor as “empty”, allowing binning to continue; rendering geometry binned for the selected tile which frees binning memory associated with this tile as it is processed; storing the results of the rendering process into memory; binning restore commands for the selected tile; and continuing binning.
These and other features and advantages of the present invention will be better understood with reference to the detailed description below and the accompanying diagrams.
REFERENCES:
patent: 5920687 (1999-07-01), Winner et al.
patent: 6279080 (2001-08-01), DeRoo
patent: 6424345 (2002-07-01), Smith et al.
Garlick Benjamin J.
Gupta Sanjay O.
Heeschen Scott C.
Hutchins Edward
Zhu Ming Benjamin
Bella Matthew C.
NVIDIA Corporation
Singh Dalip K
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