Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2001-08-02
2003-01-21
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S087000, C326S032000
Reexamination Certificate
active
06509757
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to variable impedance output drivers in integrated circuits, and more particularly to a binary weighted thermometer code for controlling the output impedance of integrated circuit output drivers due to variations in manufacturing process, voltage, and temperature.
BACKGROUND OF THE INVENTION
Integrated circuits are commonly packaged as chips. An integrated circuit within a chip communicates with the world outside the chip through metalization layers on the outside of the chip known as signal pads. In order for an integrated circuit within the chip package to send signals outside of the chip, “driver circuits” drive signals onto the signal pads on the exterior of the chip. The signal pads of various chips are connected together by transmission lines known as signal traces, thereby allowing communications between different chips.
The signal pads on a chip are connected to the packaging of the chip (e.g., a pin) which is then connected to a signal trace on a printed circuit board which runs to another integrated circuit chip or electronic device. The electrical connection of the signal pad through the packaging of the chip to the signal trace is characterized by parasitic resistance, inductance, and capacitance which interferes with the transmission of the signal from the signal pad. The transmission line characteristics of the printed circuit board signal trace itself, including parasitic resistance, capacitance, and inductance, also interfere with the quality of the transmission of the signal from the signal pad. All of the foregoing add to the load impedance which must be driven by the output driver circuit.
Due to the parasitic resistance, capacitance, and inductance which is present on chip-to-chip signal interconnections, the driver circuits that drive those signal interconnections are preferably designed to avoid excessive voltage swings when switching occurs (particularly for high speed or low power I/O). Excessive voltage swings are known as ringing. Ringing must be avoided while still switching as fast as possible to meet the high speed performance requirements of modern integrated circuits.
As known by those skilled in the art, it is important to match the output impedance of a given signal driver to the characteristic impedance of the transmission line it drives in order to avoid signal reflections due to voltage level switching on the pad, and therefore undesirable signal degradation.
Matching the impedance of an output driver to the characteristic impedance of the signal transmission line is problematic for several reasons. First, process variations inherent in the manufacturing process of integrated circuits, such as the transistor implanting doping level, the effective length of channels in the field effect transistors (FETs), the thickness of the gate oxide for transistors, and the diffusion resistance, can cause the output impedance of two supposedly identical circuits to differ. In particular, variations in any or all of the above process parameters can cause different integrated circuits intended to perform the same function to be classified as “slow”, “nominal”, or “fast”. In other words, two supposedly identical integrated circuits can vary in any or all of the process parameters. As these parameters approach the fast case, the resistance of many components within a chip is decreased. In the opposite extreme, as the process parameters stray further and further from the ideal case, the performance of the chip is degraded, specifically, the resistance of the many components within the chip is increased. This situation is referred to as the “slow” case.
In addition, variations in voltage and temperature can cause variations in the output impedance of a given chip. Specifically, the driver output impedance can vary significantly between variations in the operating voltage even within a small operating voltage tolerance range. In another example, when the temperature of an integrated circuit approaches its maximum operating temperature, the resistance of the integrated circuit components increases.
In view of the above, variable impedance output drivers have been developed to allow adjustment of the driver output impedance due to variations in manufacturing process, voltage, and temperature.
One prior art technique for accomplishing impedance matching of output pads for integrated circuits is described in U.S. Pat. No. 6,118,310 to Esch, Jr. and assigned to the same assignee of interest, entitled “Digitally Controlled Output Driver and Method for Impedance Matching”, herein incorporated by reference for all that it teaches. In the technique described therein, output driver impedance matching is accomplished by programmably enabling a combination of FETs arranged in parallel whose combined impedance closely matches the characteristic impedance of the transmission line.
Such prior art variable impedance output drivers typically use a pure thermometer code for the PVT impedance matching control in order to limit the change in output impedance when the PVT control code is updated. In particular, the impedance networks implement a “thermometer” code whereby when an nth-order signal W
n
is activated (set to “1”) all of the lower-order signals W
1
to W
n−1
are also activated. In a pure thermometer code impedance matching circuit, a first FET leg is activated and then each subsequent FET leg is activated until the desired output impedance is achieved. Accordingly, at least one leg is always activated to ensure that during the switching of FET legs on or off, the FET legs are never switched from all off to all on or vice versa, which would result in a spike in the output impedance. Table 1 illustrates a pure 11-bit thermometer code, wherein each bit 0::10 in the code word W represents an incremental admittance step of 10%.
TABLE 1
Admittance
Impedance
W
0
W
1
W
2
W
3
W
4
W
5
W
6
W
7
W
8
W
9
W
10
(Y = 1/Z)
(Z)
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1 + .1
.909
1
1
1
0
0
0
0
0
0
0
0
1 + .2
.833
1
1
1
1
0
0
0
0
0
0
0
1 + .3
.769
1
1
1
1
1
0
0
0
0
0
0
1 + .4
.714
1
1
1
1
1
1
0
0
0
0
0
1 + .5
.667
1
1
1
1
1
1
1
1
0
0
0
1 + .6
.625
1
1
1
1
1
1
1
1
1
0
0
1 + .7
.588
1
1
1
1
1
1
1
1
1
1
0
1 + .8
.555
1
1
1
1
1
1
1
1
1
1
1
1 + .9
.526
In illustrated in the example thermometer code of TABLE 1, the controllable range of sensitivity of output impedance is limited to between 1 and 0.526, wherein the admittance is changed by 0.1 or 10% for each step. As also illustrated by TABLE 1, a pure thermometer code requires one bit for each step. Accordingly, one of the drawbacks of a pure thermometer code is the large number of bits (and therefore control lines) required to allow a large range of output impedance. The number of control lines increases exponentially as the degree of required step sensitivity increases. For example, if it would be desirable to step the admittance only 1% in order to increase the sensitivity of each step, the PVT control circuit would require 101 control lines, or tenfold the number of lines required for adjusting it to the nearest 10%. Alternatively, if it were desired to increase the range of adjustable output impedance from 1 to 0.25, in the example of TABLE 1 with each step changing the admittance by 10%, an additional twenty bits (control lines) would be required.
Accordingly, although an increased sensitivity range for adjusting the PVT output impedance is desirable, the number of bits required to implement any significant range of sensitivity using a pure thermometer code is outweighed by the added design complexity and chip real estate required to implement it.
An alternative solution to the problems inherent with a pure thermometer code is the use of a pure binary weighted code whereby each leg of the PVT control circuit comprises a resistive device having an admittance corresponding to a combination of its binary weighted bit position. In other words, each leg has an admittance of 2
(bit position)
Y, where Y is a predefin
Agilent Technologie,s Inc.
Tokar Michael
Tran Anh Q.
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