Binary weighted reference circuit for a variable impedance outpu

Details Binary weighted reference circuit for a variable impedance outpu Binary weighted reference circuit for a variable impedance outpu

1994-07-06

1995-10-10

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

326 83, 326 87, H03R 190185

Patent

active

054574072

ABSTRACT:
An output buffer comprises a reference circuit having a plurality of reference transistors connected in parallel to each other and a output driver circuit having a corresponding plurality of driver transistors connected in parallel with each other. The reference transistors and the driver transistors both have varying widths with the widths of the reference transistors being a binary fraction, for instance one fourth, smaller than the widths of the corresponding output driver transistors. The transistors in the reference circuit are selectively conducted in order to match an impedance of the reference transistors to the impedance of a user selected resistor, representing a fraction of the impedance of a transmission line. The selection of the reference transistors also determines the selection of the driver transistors and consequently causes the impedance of the output driver to match the impedance of the transmission line. The reduction of the reference circuit by the binary fraction reduces the size of the overall circuit, lowers power consumption, and allows a matched layout between the transistors of the output driver and the reference circuit.

REFERENCES:
patent: 4719369 (1988-01-01), Asano et al.
patent: 5107230 (1992-04-01), King
patent: 5134311 (1992-07-01), Biber et al.
patent: 5162672 (1992-11-01), McMahan et al.
patent: 5371420 (1994-12-01), Nakao

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