Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-11-08
2003-06-10
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S375000, C327S012000, C327S043000
Reexamination Certificate
active
06577694
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to data transmission and communication systems, and more particularly to a phase detector used in a clock recovery system for recovering a clock signal from transmitted NRZ (non-return-to-zero) data. Also, the phase detector of the present invention provides the retimed or regenerated data directly from the transmitted NRZ data utilizing the recovered clock signal.
2. Description of the Related Art
When data are transmitted over a communication link, the associated clock signal is generally not transmitted, thereby providing for better efficiency of the link. However, the clock signal is necessary to retime or regenerate the received data which is typically corrupted by noise due to the physical medium and electronic and/or optical devices in the case of a transmission over an optical (e.g., glass) fiber. The clock signal also provides timing necessary for subsequent digital circuitry such as demultiplexers or framers. Therefore, transmission systems generally require that the clock signal at the receiving end of the link be extracted from the incoming data signal.
In the conventional systems, two main techniques are usually used for clock recovery. That is, direct extraction techniques and phase-locked loop (PLL) techniques are used.
In a direct extraction scheme, a high Q bandpass filter is required among other circuits. However, these high Q bandpass filters are generally expensive and limit the link to work only at a single data rate. Also, direct extraction techniques are difficult to integrate therein. In that case, phase shifters are used to ensure adequate alignment between the extracted clock and the received data. This alignment is temperature- and process-dependent and will vary depending on the circuitry used.
In PLL techniques, a reference clock is generated at the frequency of the received data usually using a voltage-controlled oscillator (VCO). A phase detector circuit compares the phase angle between the VCO clock signal and the received data stream. The phase detector provides a control signal which is a function of the relative phase between the VCO clock signal and the received data signal. This control signal is used to adjust the VCO frequency until the clock signal is synchronized with the received data.
The phase detector (PD) is a key circuit for clock and data recovery applications using PLL techniques, especially when the timing becomes critical as the data rate increases. As frequencies become higher, time delays inherent in digital circuits become more significant compared to the bit interval. The bit error rate (BER) of a transmission system (e.g., a measure of the number of erroneous data bits received divided by the total number of data bits received in a specified transmission time) is very dependent on the quality of the extracted clock by timing jitter, and also on how well the extracted clock signal is properly aligned with the received data.
To ensure optimum bit error rate when sampling the received data with the extracted clock for data regeneration, it is desirable to sample at the midpoint of each bit interval. At very high speeds (e.g., a few GHz to tens of GHz), a misalignment of even a few picoseconds can dramatically increase the transmission system's bit error rate.
Two main PD circuits (e.g., linear PDs and binary PDs) are usually used in clock and data recovery applications. Linear PDs may not work well at extremely high bit rates because they must generate relatively narrow pulses compared to the bit interval as the phase error becomes smaller. Consequently, they suffer from a relatively large static phase error which is not desirable for optimum sampling of the received data. Binary PDs (e.g., also known as “bang-bang” PDs or “earlyllate” PDs) can generate a much smaller static phase error as compared to linear PDs.
A desirable feature to enhance the clock and data alignment is that the retiming decision circuit, used to regenerate the received data, be fully part of (e.g., integrated with) the PD operation. That is, no phase adjustment is required if the PD automatically aligns the extracted clock with the received data such that the sampling of the data occurs at the midpoint of each bit interval. Therefore, no sensitive phase adjustment is required.
Presently, complex PD architectures are used to ensure optimum sampling of the received data. For high speed applications, these complex architectures have two major drawbacks: power consumption and layout complexity. Indeed, circuit performance is very sensitive to layout parasitics at high frequency operation. The parasitic elements associated with interconnect wires cause loading and coupling effects that degrade the frequency behavior and the noise performance of the circuits. Moreover, clock distribution within the PD circuit also must be carefully considered during layout design.
Therefore, a simple and efficient PD is required, especially when targeting very high data rate transmission applications. Hitherto the present invention, such a simple and efficient PD has not been developed or achieved.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional methods and structures, an object of the present invention is to provide a method and circuit for a phase detector used in phase-locked loops (PLLs) for clock and data recovery from a random NRZ data signal.
In a first aspect of the invention, a phase detector, includes a first flip-flop for sampling an incoming data signal in accordance with a local clock signal to produce a first sampled data signal, a second flip-flop for sampling the incoming data signal in accordance with the local clock signal to produce a second sampled data signal, and a third flip-flop for sampling the second sampled data signal with the first sampled data signal, to produce a binary control signal.
In a second aspect of the invention, a phase detector circuit is provided which is used in a clock and data recovery system for synchronizing a received non-return-to-zero (NRZ) data signal with a clock signal generated by a clock source, the clock signal having a period equal to the unit bit interval of the received NRZ data signal, the phase detector for regenerating the received NRZ data signal using the clock signal. The phase detector includes a first flip-flop, including data and clock input terminals for respectively receiving a data input and a clock: input, and an output terminal for providing an output, a second flip-flop, including data and clock input terminals for respectively receiving the data input and an inverted clock input, and an output terminal for providing an output, and a third flip-flop, including data and clock input terminals for respectively receiving an output from the second flip-flop and an inverted output from the first flip-flop, and an output terminal for providing an output.
In a third aspect of the invention, a phase detector includes a data signal input for supplying input data and opposite phase input data of said input data, a clock signal input for supplying an input clock and an opposite phase input clock of the input clock, a first flip-flop, including differential data D and DB input terminals, differential clock C and CB input terminals and differential Q and QB output terminals, the first flip-flop receiving input data at the differential data input terminals and the input clock at the differential clock input terminals, a second flip-flop, including differential data D and DB input terminals, differential clock C and CB input terminals and differential Q and QB output terminals, the second flip- flop receiving input data at the differential data input terminals and the input clock at the differential clock input terminals; and a third flip-flop, including differential data D and DB input terminals, differential clock C and CB input terminals and differential Q and QB output terminals, the third flip-flop receiving a differential output from the secon
Dang, Esq. Thu Ann
McGinn & Gibb PLLC
Pham Chi
Tran Khanh Cong
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