Binary data memory design with data stored in low-power sense

Details Binary data memory design with data stored in low-power sense Binary data memory design with data stored in low-power sense

2000-04-18

2003-01-14

Hudspeth, David (Department: 2651)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S104000, C711S170000

Reexamination Certificate

active

06507887

ABSTRACT:

The present invention relates to data processing and, more particularly, to memories used in data processing systems. A major objective of the invention is to reduce power consumption by a computer memory and thus by an incorporating data processing system.
Much of modern progress is associated with the evolution of computers. A typical computer comprises a processor for processing data by executing instructions, memory for storing instructions and data, and various interface devices. Early computers were room-sized and required dedicated cooling systems to remove the heat generated by the power they dissipated. Advances in integrated circuit technology have provided ever-more powerful data processing systems that are smaller and consume less power than their predecessors.
Even though power requirements have decreased by orders of magnitude, power consumption remains a major concern. This is most apparent in battery-powered portable devices. People often carry extra batteries, AC adapters, and battery rechargers to ensure against a loss of functionality. Having to carry these accessories and supplies decreases the convenience of the portable devices. The need to carry extra batteries and power accessories can be obviated in part by using larger (or more) batteries, but this increases device bulk and thus decreases portability.
Reducing power requirements allows the use of smaller batteries and/or decreases the frequency with which batteries must be replaced or recharged. Using smaller batteries decreases device bulk. Reducing frequency of replacement reduces the financial and environmental cost of device ownership. Reducing the frequency of recharging extends battery life and makes it more practical to leave power accessories behind. In some cases, lower power requirements increase the viability of solar power to replace or supplement battery power, further enhancing the portability. Reducing power consumption also reduces heat dissipation, so that less bulk needs to be dedicated to removing heat from a device.
There are many approaches to reducing power requirements. Advances in semiconductor manufacturing have permitted smaller and more power efficient circuits. Advances in circuit design and processor architecture have also reduced power requirements. Such advances have reduced power requirements across all types of devices including processors, memories, and interface devices.
In addition to these hardware-oriented approaches, there are software-oriented approaches to reducing power requirements. Considerable effort has been invested in designing instruction sets and data formats for efficient use of available capacities for computation, storage and communication. As these capacities are used more efficiently, power requirements are reduced. However, as dramatic as power reductions have been to date, further reductions are desired to increase portability and convenience, reduce environmental and financial costs, and achieve other objectives.
SUMMARY OF THE INVENTION
The present invention provides a random-access binary memory design in which the sense (inverted vs. uninverted) in which data is stored and a low-power sense of the memory output are matched. For many types of memories, the power consumed as a bit of data is output depends on the value of that bit. For example, memories based on prevalent n-type insulated-gate field-effect transistor (n-type IGFET, also known as “NMOS”) technology typically apply an active high precharge to memory bit lines (to take advantage of the fact that NMOS transistors can effect downward transitions faster than upward transitions) and, therefore, consume less power when outputting a “1” than when outputting a “0”. In the case that the data to be stored contains more 0s than 1s, the present invention provides for storing the data in inverted form and then inverting the output. The invention has clearest applicability to read-only memories, but can be applied to various types of rewrittable memories.
The invention can be applied in a unitary manner to all data stored in a device. If the data to be stored is, overall, already in the low-power sense (e.g., mostly 1s), then the result is a device with data stored in its uninverted sense. If the data to be stored is, overall, in the high-power sense, the invention provides for storing the data in its inverted sense and then inverting the device output.
The advantage of the invention is greatest where the numbers of 1s and 0s stored are very different, i.e., the distribution of 1s and 0s is unbalanced. Even if the 1s and 0s are balanced overall, the invention can provide an advantage where there are local imbalances between the 1s and 0s. For example, the invention can be applied independently to each device output to achieve, in general, a greater power reduction than could be achieved by treating the device in a unitary manner.
Further reductions in power consumption are achievable in some cases by further subdividing the stored bits. A practical implementation groups bits connected to a common sense amplifier. If the data is to be inverted, then the sense amplifier can be sense inverting instead of sense preserving (or vice versa). In embodiments where the invention is not applied in a unitary manner across a device, it is possible for a device to have some inverting outputs (at either the block or device level) and some sense-preserving outputs (again, at either the block or device level).
In some embodiments, output inversion is effected by inverters external to the integrated circuit storing the data. However, it is preferable that the inversion be built into the device, e.g., as sense-inverting sense amplifiers. Alternative embodiments achieve the inversion internally by inverting the precharge (or “pre-bias”) sense (e.g., using p-type field-effect transistors and a low precharge level) as a function of the overall sense of the data, rather than the other way around.
Data weighting is provided for by the present invention. For example, some memory addresses are accessed much more frequently than others. In that case, the more frequently accessed data can be given greater weight than less frequently accessed data. Of course, it may be difficult to determine precisely the frequency with which data will be accessed. Nonetheless, even rough predictions can be helpful in optimizing a design for minimum power consumption.
The present invention provides for reduced power consumption for memory devices, and thus of incorporating systems. This data based approach to saving power is compatible with most other approaches to conserving power, including data compression and other non-data related approaches. Accordingly, the present invention provides for a power reduction that is cumulative to that provided by other approaches. Thus, devices with less bulk and/or longer periods between recharging and/or battery replacement are made possible. This extends the range of devices that can be made portable and increase the convenience of device types that have been made portable. These and other features and advantages of the invention are apparent from the description below with reference to the following drawings.


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