Binary controlled phase selector with output duty cycle...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C375S226000, C375S362000, C327S144000, C327S141000, C327S147000, C327S151000

Reexamination Certificate

active

07613266

ABSTRACT:
A phase selection circuit having a selection circuit, binary weighted current sources, and an amplifier circuit. The phase selection circuit is configured for selecting adjacent phase signals from a number of equally-spaced phases of a clock signal, based on a phase selection value. The selection circuit outputs the adjacent phase signals to respective first and second binary weighted current sources, along with a digital interpolation value. The first current source outputs a contribution current onto a summing node based on the first adjacent phase signal and the digital interpolation control value, and the second current source outputs a second contribution current to the summing node based on the second adjacent phase signal and an inverse of the digital interpolation control value, resulting in an interpolated signal. An amplifier circuit outputs the interpolated signal as a phase-interpolated clock signal according to the phase selection value.

REFERENCES:
U.S. Appl. No. 11/033,755, filed Jan. 13, 2005, Talbot et al.
U.S. Appl. No. 11/033,758, filed Jan. 13, 2005, Talbot.
“AMD-3181™ HyperTransport™ PCI-X® Tunnel Data Sheet”, 24637 Rev. 3.02, Aug. 10, 2004, pp. 1-87.

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