BiMIS logic circuit

Details BiMIS logic circuit BiMIS logic circuit

1993-10-01

1995-10-10

Westin, Edward P.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar and fet

326110, H03K 1902

Patent

active

054574137

ABSTRACT:
A BiMIS circuit has first and second input terminals; first and second output terminals; a first bipolar transistor having a collector receiving a first potential, an emitter connected to the first output terminal, and a base connected to the second output terminal; a second bipolar transistor having a collector connected to the first output terminal and an emitter receiving a reference potential; a first MIS transistor circuit including MIS transistors, connected to the base and the collector of the first bipolar transistor and the first input terminal, and turned on or off depending on a potential of the first input terminal; and a second MIS transistor circuit including MIS transistors, connected to the base of the first bipolar transistor, the second input terminal and the base of the second bipolar transistor, and turned on or off depending on a potential of the second input terminal. The BiMIS circuit includes at least one of: a capacitor having one terminal connected to the first input terminal and the other terminal connected to the base of the second bipolar transistor; a discharging circuit connected to the base of the first bipolar transistor for discharging the base; and a potential setting circuit connected to the base of the second bipolar transistor for setting a potential of the base at a predetermined level.

REFERENCES:
patent: 4804869 (1989-02-01), Masuda
patent: 4977337 (1990-12-01), Ohbayashi
patent: 5001366 (1991-03-01), Masuda
patent: 5164617 (1992-11-01), Hanibuchi
patent: 5206546 (1993-04-01), Usami
patent: 5313116 (1994-05-01), Murabayashi

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