Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1997-08-11
2001-05-01
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S168000, C711S154000, C711S211000
Reexamination Certificate
active
06226723
ABSTRACT:
PAPER APPENDIX
A Paper Appendix of an IEEE draft standard P1596.7-199X including an embodiment of the invention comprising sixty-seven sheets is included herewith and incorporated by reference in its entirety for all purposes.
BACKGROUND OF THE INVENTION
The present invention relates to computer memories. More particularly, the present invention pertains to an improved memory interface particularly useful for dynamic random access memories and communication protocols therefor.
There is a constant need to increase the performance of various types of memories employed in computers, particularly dynamic random access memory (DRAM) devices. In a typical DRAM, shown in
FIG. 1
, digital information, or data, is stored in an arrangement of memory cells
3
, configured in a matrix of intersecting rows
5
and columns
6
. The rows
5
may be referred to as word lines
5
. Each memory cell comprises a storage capacitor (not shown) capable of holding a charge and a metal-oxide semiconductor field effect transistor (MOSFET) (not shown) for accessing the capacitor charge; hereinafter this transistor is referred to as an access transistor. The charge is a voltage potential referred to as a data bit and is typified as either a high voltage or a low voltage. Therefore, the memory has two states, often thought of as the true logic state and the complementary logic state. The data bit is amplified and latched to the digit lines
7
by a sense amplifier
8
.
There are two operations available in the DRAM memory; a bit of data may be stored in a specific cell in the write mode, or a bit of data may be retrieved from a specific cell in the read mode. The data is either transferred from the digit lines
7
to Input/Output lines (I/O)
9
in the read mode; or transferred from the I/O lines
9
to the digit lines
7
in the write mode. In either case, the data is transferred through MOSFETs
10
used as switching devices and called decode transistors. For each bit of data stored, its true logic state is available at a first I/O line
11
and its complementary logic state is available at a second I/O line
13
, designated I/O complement. For purposes of this discussion, I/O and I/O complement lines are often referred to as just I/O lines
9
. Although each cell
3
is only connected to one digit line
7
through an activated access transistor, each cell
3
is electrically referenced to two digit lines
7
, referred to as a digit line pair
15
, through the sense amplifiers
8
. The digit line pair
15
comprises the “digit line”
17
for coupling true data and the “digit bar line”
19
for coupling complementary data. Typically, the digit line
17
is referred to as digit and the digit bar line
19
is referred to as digit bar. The digit line pair
15
couples the true and complementary data between the selected cell
3
and the I/O lines.
In order to read from or write to a cell
3
, the particular cell
3
in question must be selected or sometimes referred to as “addressed.” In addition, control information must be received from a controller (not shown), such as a CPU, to indicate whether a write operation or a read operation is to occur. A row
5
of cells
3
is selected and connected to the sense amplifier
8
when the row decoder
21
activates the word line
5
. The column decoder
23
connects a subset of the sense amplifiers
8
to the I/O lines of the memory.
Prior art attempts to enhance the performance of a DRAM memory, such as the one shown in
FIG. 1
, has involved routing control and data information on differing bus architectures. One attempt involves transmitting read and write data over separate data lines, typically referred to as a separated I/O type of semiconductor memory. Examples of a separated I/O memory as disclosed in U.S. Pat. No. 5,323,349 to Hamade et al., U.S. Pat. No. 5,307,314 to Lee, and U.S. Pat. No. 4,954,992 to Kumanoya et al. As described in those patents, separated I/O memory is typically employed on a dynamic random access memory (DRAM).
In the I/O separated memory, the control and address information are on communication lines which are separate from the data lines. A variation of the previously described separated I/O memory involves using a common uni-directional bus for control and data information transmitted to the DRAM. A second uni-directional bus is employed to transmit data information coming from the DRAM. This provides good performance for a relatively uniform mix of read and writes, but performance degrades rapidly for long sequences of either reading or writing data, which occurs commonly. One of the busses is substantially underutilized, resulting in a reduction in throughput.
Another attempt at enhancing the performance of a DRAM involves having a bi-directional bus on which all the data information and control information are transmitted. This requires time multiplexing the transmission of the control information, the address information and the data, reducing the effective throughput of the device well below the bandwidth limit of the bus and increasing the power consumed to effectuate data transfers.
What is needed, therefore, is a computer memory device that more efficiently utilizes bus bandwidth during read and write operations, while reducing the power consumed to achieve the same.
SUMMARY OF THE INVENTION
A computer memory device features a high-bandwidth memory interface to transfer information between a controller and the memory cells of a memory module. Bifurcated communication busses are provided to take advantage of the memory interface. One of the busses, dataLink, is dedicated to data information transfer, between the controller and the memory modules, with the remaining bus, commandLink, being dedicated to command/address information transfer therebetween. This facilitates communication between the controller and the memory modules using information packets, bifurcated into data packets and command/address packets. To that end, the interface circuitry includes encoded chip select techniques that employs slaveId comparison logic, a plurality of control registers and delay registers to regulate the synchronization of communication transfers over the commandLink and the dataLink, as well as a queue register in which the packets are temporarily stored. The packets are scheduled to be placed on the appropriate busses so as to maximize data transfer, while minimizing power consumption of the memory device. Synchronization of the communication transfers on the commandLink and the dataLink is achieved during initialization of the memory device and may be periodically checked during normal operations, without degrading transfer throughput. In this fashion, the memory device may be easily scaled so that variable bandwidth data transfers may be provided while maximizing the quantity of data transferred on the dataLink and reducing the power necessary to achieve the same.
Typically, the computer memory device includes an array of memory modules. Each of the memory modules includes a matrix of memory cells and a plurality of data transfer ports, a plurality of control transfer ports, with the high-bandwidth memory interface coupled between the matrix of memory cells and the plurality of data and control transfer ports. The data transfer ports may be separate input/output ports or a port which handles both data input and data output. The controller has a system input port for receiving information from a central processing unit, CPU, and a plurality of data output ports, as well as a plurality of control/address output ports. The data output ports and the control/address output ports are in signal communication with the array of memory modules via the dataLink and the commandLink, respectively. Specifically, the dataLink is coupled between the data transfer ports and the data output ports, and the commandLink is coupled between control transfer ports and the control output ports. The commandLink is connected so that one of the plurality of control transfer ports of each of the memory modules is connected in common to receive, concurrently,
Gustavson David B.
James David V.
Wiggers Hans A.
Advanced Memory International, Inc.
Fliesler Dubb Meyer & Lovejoy LLP
Kim Matthew
Tzeng Fred F.
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