Patent
1986-05-30
1987-02-03
Larkins, William D.
357 238, 357 2314, H01L 2978, H01L 2908, H01L 2944
Patent
active
046411640
ABSTRACT:
A vertical MOSFET in a silicon wafer having opposing major surfaces includes a source electrode on one surface, a drain electrode on the second surface, and an internally disposed insulated gate. The silicon between the insulated gate and each of the major surfaces is of first conductivity type and the silicon that is laterally adjacent to the insulated gate is of second conductivity type, such that a predetermined voltage on the insulated gate creates an inversion channel extending a predetermined distance into the laterally adjacent silicon. That portion of the laterally adjacent silicon where the inversion channel is formed is of relatively lightly doped material, whereas other areas of the laterally adjacent silicon is relatively heavily doped. The silicon that is between the insulated gate and each wafer surface includes a relatively lightly doped voltage-supporting region contiguous with the insulated gate and the laterally adjacent silicon and a relatively heavily doped region between this voltage-supporting region and the surface. Additionally, the interface between the insulated gate and the laterally adjacent silicon has a low density of interface states.
REFERENCES:
patent: 4062036 (1977-12-01), Yoshida
patent: 4249190 (1981-02-01), Cho
patent: 4297718 (1981-10-01), Nishizawa et al.
patent: 4378629 (1983-04-01), Bozler et al.
patent: 4530149 (1985-07-01), Jastrzebski et al.
patent: 4546375 (1985-10-01), Blackstone et al.
patent: 4549926 (1985-10-01), Corboy, Jr. et al.
patent: 4554570 (1985-11-01), Jastrzebski et al.
patent: 4586240 (1986-05-01), Blackstone et al.
Fabrication and Numerical Simulation of the Permeable Base Transistor, C. O. Bozler et al., IEEE Transactions On Electron Devices, vol. ED-27, No. 6, Jun. 1980, pp. 1128-1141.
Dolny Gary M.
Goodman Lawrence A.
Cohen Donald S.
Glick Kenneth R.
Lamont John
Larkins William D.
Morris Birgit E.
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