Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2003-03-21
2004-11-02
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S062000
Reexamination Certificate
active
06812741
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bidirectional signal transmission circuit and a bus system for facilitating impedance matching and fast signal transfer.
2. Description of the Prior Art
As MPUs and memory devices become faster, the demand for speeding up data transfer on buses is growing in recent years. However, such speedups also incur difficulties in the proper transfer of data. This is because disturbances such as reflections of signals due to a mismatch with a characteristic impedance of a transmission line and crosstalk between adjacent lines become more serious with increase in data transfer rate.
To avoid such unwanted signal reflections, impedance matching is commonly performed by means of series termination that inserts a resistor in series with a transmission line or parallel termination that inserts a resistor between a transmission line and a power or ground plane.
The series termination couples a resistor in series between an output buffer (a driver) and a transmission line, to match the output impedance with the transmission line impedance and reduce the output amplitude. When the transmission line is unidirectional, placing the resistor on the output line (i.e. at the output port or terminal) of the output buffer is effective. The unidirectional transmission line referred to here is a transmission line that transmits signals only in one direction.
FIG. 1
shows an example circuit where series termination is applied to an unidirectional transmission line. To eliminate an impedance mismatch between an output buffer
801
and a unidirectional transmission line
803
coupled thereto, a resistor
804
is positioned in series between the output buffer
801
and the unidirectional transmission line
803
. Let Ro
1
be the output resistance of the output buffer
801
, Zo be the characteristic impedance of the unidirectional transmission line
803
, and Rs
1
be the value of the resistor
804
. Then Rs
1
is determined by the equation Rs
1
=Zo−Ro
1
, to match the output impedance (Rs
1
+Ro
1
) with the transmission line impedance (Zo) (i.e. to establish the relation Rs
1
+Ro
1
=Zo). Thus, the resistor
804
serves to match the impedance of the output buffer side (output impedance) to that of the unidirectional transmission line side at a junction between the resistor
804
and the transmission line
803
.
However, the above series termination is not applicable to a bidirectional transmission line that transmits signals in two directions, because in the case of the bidirectional transmission line its both ends will act as output ends as well as input ends.
FIG. 2
shows an example circuit where a resistor is series-connected to one end of a bidirectional transmission line. Suppose Rs
1
of a resistor
906
is determined in the same way as FIG.
1
. When transmitting a signal from an output buffer
901
, an output impedance and an impedance of a bidirectional transmission line
905
match. However, when transmitting a signal from an output buffer
903
, an impedance mismatch occurs due to the absence of a series terminating resistor between the output buffer
903
and the bidirectional transmission line.
905
, as a result of which signal reflections arise.
Several impedance matching methods for bidirectional transmission lines have been devised in recent years through the use of various bus topologies and termination techniques. Examples of such methods are RSL (Rambus Signaling Logic) proposed by Rambus, Inc. and SSTL (Stub Series Terminated Logic) [EIAJED-5512] standardized by the Electronic Industries Association of Japan.
FIGS. 3 and 4
show example circuits that employ RSL and SSTL, respectively. In the figures, a portion enclosed by a dashed line shows a pair of an output buffer (a driver) and an input buffer (a receiver) in greater detail. The output buffer in
FIG. 3
is an open drain output, whereas the output buffer in
FIG. 4
is a tri-state output.
RSL in
FIG. 3
is characterized by a restricted bus topology where single-stroke configuration with no branch lines is adopted to a bus line, in order to ensure impedance matching. In SSTL in
FIG. 4
, on the other hand, a bus line is parallel terminated and series terminating resistors are arranged at branch points of lines branched from the bus line, to match the branch lines to the bus line. Thus, SSTL enables impedance matching for a bus topology that has branch lines.
However, with conventional bus interfaces, it is becoming increasingly difficult to improve clock frequencies for faster signal transmission and at the same time ensure impedance matching.
In the case of RSL in
FIG. 3
, when mounting an LSI (Large-Scale Integration) onto a board, leads included in the LSI package will end up being branch lines, so that it is impossible to form a bus line of single-stroke configuration which contains no branch lines. Though such a bus line can operate without problems within a frequency range up to the order of some hundreds of megahertz, at higher frequencies (the order of gigahertz) the bus line inevitably suffers signal reflections because of the presence of several branch lines (leads) which do not match with the bus line.
In the case of SSTL in
FIG. 4
, the series terminating resistors arranged at the branch points serve to match impedances when signals are transmitted from the branch lines to the bus line (output onto the bus line) but not when signals are transmitted from the bus line to the branch lines (input from the bus line). Therefore, such a bus line also suffers signal reflections at high frequencies (the order of gigahertz).
SUMMARY OF THE INVENTION
The first object of the invention is to provide a bidirectional signal transmission circuit that ensures impedance matching and fast signal transmission without restrictions on bus topology, regardless of in which direction a signal is to be transmitted.
The second object of the invention is to provide a bus system that facilitates impedance matching and fast signal transmission.
The third object of the invention is to provide a bus interface that delivers high noise immunity in addition to the above stated effects.
The first and second objects can be fulfilled by a bidirectional transmission circuit for inputting/outputting a signal from/onto a bidirectional transmission line, including: a transceiver for transmitting/receiving a signal; a first element having an impedance; a second element being a short line; and a switching unit for coupling the transceiver to the bidirectional transmission line via the first element when the transceiver transmits a signal, and coupling the transceiver to the bidirectional transmission line via the second element when the transceiver receives a signal.
With the above construction, the impedance on the side of the transceiver varies from the time of signal transmission by the transceiver to the time of signal reception by the transceiver. Accordingly, the transceiver and the bidirectional transmission line can easily be matched regardless of whether the transceiver transmits or receives a signal, and the signal transfer can be accelerated.
Here, a combined impedance of an output impedance of the transceiver and the impedance of the first element may match a characteristic impedance of the bidirectional transmission line.
Here, the first element may be a resistor.
With the above construction, the first element with the proper impedance can easily be realized by means of a resistor, and the second element can easily be realized by means of a wire or a pattern on a printed board.
Here, the first element may be a driver that amplifies an output current of the transceiver.
With the above construction, the impedance matching is ensured by matching the transceiver to the bidirectional transmission line or by matching the bidirectional transmission line to the transceiver. Further, even when the current drive ability of the transceiver is low, such a drive ability is appropriately adjusted by equipping with a driver that has a
Fukumoto Yukihiro
Saito Yoshiyuki
Shibata Osamu
Chang Daniel D.
Matsushita Electric - Industrial Co., Ltd.
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