Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – In integrated circuit
Reexamination Certificate
2003-08-26
2004-12-28
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
In integrated circuit
C257S330000
Reexamination Certificate
active
06835993
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor devices and more specifically relates to lateral conduction and bidirectional conduction superjunction devices.
BACKGROUND OF THE INVENTION
MOSFET superjunction devices are well known and are disclosed in U.S. Pat. Nos. 4,754,310 and 5,216,275 and in a publication entitled “Simulated Superior Performance of Semiconductor Superjunction Devices” by Fujihara and Miyaska in the Proceedings of 1998 International Symposium on Semiconductor Devices & ICs, pages 423 to 426. Such superjunction devices have required deep trenches or sequentially deposited and diffused P and N epitaxially layers of silicon for their production.
Superjunction devices also frequently employ deep spaced pillars of semiconductor material of one conductivity in a substrate of the opposite conductivity type. The total charge of the pillars is matched to that of the surrounding substrate in which they are received to enable the use of a high concentration substrate which has a reduced R
DSON
in forward conduction, while blocking is obtained by equally depleting out charge from substrate and pillars. A conventional DMOS gate structure is used to turn the device on and off.
It would be desirable to make a superjunction device of simpler structure to enable the use of a simpler manufacturing process than that used to form the deep spaced pillars; and to make a device that can be bidirectional and capable of blocking voltage applied to either the source or drain, relative to the other terminal. It would also be desirable to have such a device which does not require a termination structure.
BRIEF SUMMARY OF THE INVENTION
In accordance with the invention, a novel device structure which is symmetric and in which the source and drain terminals are interchangeable is provided. The source and drain terminals are placed within regions which are capable of supporting high reverse voltage as well as possessing low resistivity. Current flow in the channel region which is between these regions is controlled by a gate electrode.
In a first embodiment, the device employs laterally extending parallel spaced vertical trenches with sidewall diffusions which are easily fabricated.
In a second embodiment, lateral interleaved layers of N and P materials and a trench gate are used. The layers can be formed by successive depositions of N or P epitaxial silicon, each layer being diffused with the opposite conductivity type. No masking is needed for these steps, and no termination structure is needed. Thus, the semiconductor drift region comprises alternate N-type and P-type regions one on top of the other to allow high voltage blocking during the blocking mode while permitting low resistance to current flow during the conduction mode.
In a bidirectional embodiment, capable of blocking voltage applied to either the drain or source terminal relative to the other, the device structure is symmetric in which the source and drain terminals are interchangeable. The source and drain terminals are placed within regions which are capable of supporting high reverse voltage as well as possessing low resistivity. A gate electrode controls current flow into the drift region.
REFERENCES:
patent: 4754310 (1988-06-01), Coe
patent: 6509220 (2003-01-01), Disney
patent: 6566709 (2003-05-01), Fujihira
patent: 6787872 (2004-09-01), Kinzer et al.
Xu, S., et al., “120 V Interdigitated-Drain LDMOS (IDLDMOD) on SOI Substrate Breaking Power LDMOS Limit”, Oct. 2000, IEDM 2000, pp. 1980-1985.
Kinzer Daniel M.
Sridevan Srikant
International Rectifier Corporation
Ostrolenk Faber Gerb & Soffen, LLP
Weiss Howard
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