Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-12-21
2003-02-04
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S090000, C326S083000, C326S021000, C710S120000
Reexamination Certificate
active
06515515
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This disclosure relates to a data path circuit and method and, more particularly, to a circuit for bidirectional data transfer for increasing a bandwidth of information exchanged between a plurality of entities.
2. Description of the Related Art
Metal interconnect adds significantly to the cost of VLSI circuits. Wiring resources are constrained either by the cost of additional wiring levels or by the improvements in process and lithography required to increase wiring density. One way to better utilize the scarce wiring resource is to share bus wires between macros. For chip to chip communications, a prior art approach described in U.S. Pat. No. 5,604,450 by Borkar et al. achieves bidirectional signaling by employing a ternary encoding scheme. While this scheme may achieve higher throughput at the board level, it comes at great expense to be deployed for chip (unit/macro) level wire interconnect. A more satisfactory solution is desirable which neither degrades signal noise margin nor consumes DC power.
A shared bus, or what is called a tristate bus, enables more than one sending entity to control the state of the bus. Unfortunately, in most tristate bus schemes, a signal wire can only transfer one bit of information each cycle. Each sending entity must time share a bus with the other sending entities using that same bus, otherwise, logic conflicts would arise between a driver trying to pull a net low to a “0” and another trying to pull the same net high to a “1”. Hence in all the above mentioned schemes, only one driver can be active during any given cycle; the other drivers attached to the net are put into a high impedance state. While a shared bus scheme may save wiring resources, it does not increase the potential throughput, or bandwidth, of the bus. To achieve improved bandwidth, the bus must be time shared over a single cycle.
Therefore, a need exists for a circuit, which could be inserted near the center of a bus for exchanging data on bus wires connecting two or more entities in such a way that two waves of data, moving in opposite directions, may simultaneously exist on the bus without colliding data.
SUMMARY
A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for sending and receiving data to each other. An at least one swapper circuit is electrically connected to the bus at a connection point between the plurality of entities. The at least one swapper circuit includes means for timing data transfer between a send data mode and a receive data mode and sending and receiving data during the respective modes. The at least one swapper circuit may include a routing means for receiving data simultaneously from the plurality of entities and then sending data simultaneously to the plurality of entities without colliding data. An entity timing means for each of the plurality of entities may be electrically connected to the at least one swapper circuit for propagating timing signals to the at least one swapper circuit to enable the send data mode and the receive data mode within the at least one swapper circuit to correspond with a receive data mode and a send data mode, respectively, for each entity. The timing signals may be asynchronous and timed by each of the plurality of entities. A timing means for data transfer and the entity timing means for propagating timing signals may be synchronized by a global clock signal provided thereto by a global clock. The timing signals may be propagated on at least four adjacent wires such that each wire has a timing signal opposite in polarity to the wires adjacent thereto and two internal wires have more capacitive coupling than the other wires for representing a slowest signal on the bus.
The circuit for bidirectionally exchanging data may also have the at least one swapper circuit located at a substantially equal distance along the bus from each of the plurality of entities. The plurality of entities may be components on a semiconductor device. The at least one swapper circuit may include multiple inputs for exchanging data between multiple busses. An output of the at least one swapper may be connected to one of the multiple inputs to turn the at least one swapper circuit off if no data is being transferred. The at least one swapper may include an at least one tristate driver which is switched between an active mode and a high impedance mode corresponding to the send data mode and the receive data mode of the at least one swapper. Each of the plurality of entities may include a unidirectional tristate driver cooperating with at least one latch and a timing signal generated from a global clock to sequence send data modes and receive data modes by each of the plurality of entities.
The circuit for bidirectionally exchanging data may have the at least one swapper connect to at least one bidirectional repeater for decreasing signal delay and removing noise from the bus. The at least one bidirectional repeater may include two tristate drivers, each driver having an output connected to an input of the other such that signals are driven in only one direction at a time during a predetermined period of time. The data transferred by the tristate busses may be binary signals, analog signals, differential signals or N-state signals.
A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a plurality of buses, the plurality of entities for sending and receiving data to each other, an at least one swapper circuit electrically connected to the bus at a connection point between the plurality of entities, the at least one swapper circuit including means for timing data transfer between a send data mode and a receive data mode, an at least one multiplexor connecting to the plurality of busses and to the at least one swapper for receiving data from the plurality of entities on one bus and for sending data through another bus to the plurality of entities, entity timing means for each of the plurality of entities electrically connecting to the at least one swapper circuit for propagating timing signals to the at least one swapper circuit to enable the send data mode and the receive data mode within the at least one swapper circuit to correspond with a receive data mode and a send data mode, respectively, for each entity and the at least one swapper circuit including a routing means for receiving data simultaneously from the plurality of entities and then sending data simultaneously to the plurality of entities without colliding data.
The multiplexor may include a plurality of legs, each leg further including a pair of NFETs. An arbitration circuit may be electrically connected to arbitration latches for exchanging information among the plurality of busses. The arbitration circuit may have a first set of inputs for receiving routing request signals from the plurality of entities. The arbitration circuit may have a first set of outputs for producing acknowledge signals for indicating successful data transfer to the plurality of entities. The arbitration latches may connect to the at least one swapper circuit and to a second set of outputs of the arbitration circuit for supplying routing information from the arbitration circuit to the at least one swapper. The arbitration circuit may include logic circuitry for generating select control signals to the multiplexor and wherein the arbitration latches provide a delay to synchronize data transfer with routing information. A timing circuit for synchronizing data flow into and out of the at least one swapper and the plurality of entities may also be included. The plurality of entities may be a plurality of processors. The acknowledge signals may include data address information. The routing requests may arrive at the arbitration circuit one or more clock cycles before corresponding data to provide a predetermined amount of time to process the routing requests.
A swapper circuit for exchanging data incl
Bozso Ferenc Miklos
Emma Philip George
Reohr William Robert
F. Chau & Associates LLP
International Business Machines - Corporation
Percello Louis J.
Tan Vibol
Tokar Michael
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