Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-03-31
2003-01-28
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
06513090
ABSTRACT:
BACKGROUND
The invention relates generally to data transfer operations within a computing system and, more particularly, to bidirectional data transfer operations during bridge circuit buffer flushing operations.
In some computing systems, device may coordinate the transfer of data via a series of read and write ops through an intermediary device. One such intermediary device is a processor-to-bus bridge circuit. Referring to
FIG. 1
for example, computer system
100
includes system memory
102
, host processor
104
, bridge circuit
106
, system bus
108
, and bus device
110
. Bridge circuit
106
typically includes memory interface
112
for communicating with system memory
102
, processor interface
114
for communicating with processor
104
, bus interface
116
for communicating with bus
108
, and control circuit
118
to coordinate the transfer of information between memory interface
112
and/or processor interface
114
and bus interface
116
. Each interface within bridge circuit
106
may include one or more buffers/caches to facilitate the exchange of data through bridge circuit
106
. Bus interface
116
, for example, may include a first set of read and write buffers to facilitate data transfers between a bus device (e.g. device
110
) and system memory
112
, and a second set of read and write buffers to facilitate data transfers between a bus device (e.g. device
110
) and processor
104
.
One standard approach to exchanging data between processor
104
and bus device
110
includes the use of semaphores, which are typically stored in system memory
102
. Consider, for example, the transfer of information from processor
104
to bus device
110
. Initially, processor
104
may cause the data destined for bus device
110
to be written into a write buffer in bus interface
116
. (Data placed in a write buffer but not yet delivered to its destination is said to be “posted.”) Next, processor
104
may update one or more semaphores in system memory
102
to indicate it has completed its portion of a write-data-to-bus-device operation. If bus device
110
is allowed to read the state of those semaphores updated by processor
104
before the previously posted data is delivered, bus device
110
may incorrectly determine that the data has in fact been delivered. Such a situation can lead to data corruption.
To prevent this situation from occurring, computer system communication protocols typically enforce transaction ordering. In a computer system operating in accordance with the Peripheral Component Interface (PCI) standard for example, transaction ordering ensures that writes from one bus master (e.g. processor
104
) anywhere in computer system
100
are observable by another bus master (e.g., bus device
110
) in the order generated by the initiating bus master. (See the “Peripheral Component Interface Local Bus Specification,” Revision 2.1, 1995.)
Bridge circuits designed in accordance with PCI-type transaction ordering rules typically flush the off-device's write buffer on the occurrence of a read synchronization event. For example, if processor
104
issues a read request to bus device
110
(a read synchronization event), that write buffer within bus interface
116
associated with bus-device-to-memory data transfers may be flushed. Alternatively, if bus device
110
issues a read request to system memory
102
(a read synchronization event), that write buffer within bus interface
116
associated with processor-to-bus-device data transfers may be flushed. During a flush operation, data is transferred from the write buffer being flushed to system memory
102
(if processor
104
issued the synchronizing read request) or bus
108
(if a bus device,
110
, for example, issued the synchronizing read request). During flushing operations, control circuit
118
prevents new data from entering bridge circuit
106
. That is, while data is being flushed to system memory
102
, processor
104
and bus device
110
are blocked from transferring data to or from bridge circuit
106
. Similarly, while data is begin flushed to bus
108
, system memory
102
and processor
104
are blocked from transferring data to or from bridge circuit
106
.
Conventional buffer flushing operations tend to reduce that effective data transfer rate/bandwidth between various system components by halting some on going transfers and preventing some others from beginning. This reduction may adversely affect system performance. Thus, there is a need for techniques that flush data transfer buffers without unnecessarily restricting other data transfer operations.
SUMMARY
In one embodiment, the invention provides a computer system bridge circuit adapted to allow the bidirectional flow of data through itself during a write buffer flushing operation. In another embodiment, the invention provides a buffer structure supportive of this bidirectional flow of data. In still another embodiment, the invention provides a method by which a computer system bridge circuit may provide the aforementioned bidirectional data flow capability.
REFERENCES:
patent: 5761450 (1998-06-01), Shah
patent: 5983304 (1999-11-01), Jin
patent: 6078976 (2000-06-01), Obayashi
patent: 6247102 (2001-06-01), Chin et al.
patent: 6324612 (2001-11-01), Chen et al.
Micro)n Technology, Inc.
Nguyen Hiep T.
Trop Pruner & Hu P.C.
LandOfFree
Bidirectional data transfer during buffer flushing operations does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bidirectional data transfer during buffer flushing operations, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bidirectional data transfer during buffer flushing operations will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3018763