BiCMOS tri-state buffer with low leakage current

Details BiCMOS tri-state buffer with low leakage current BiCMOS tri-state buffer with low leakage current

1996-09-03

1998-03-10

Westin, Edward P.

Electronic digital logic circuitry

Tri-state

326 18, 326 84, H03K 1901

Patent

active

057265879

ABSTRACT:
An improved tri-state output buffer having an emitter-follower output stage clamps the reverse-bias voltage across the base-emitter path of an emitter-follower to limit the output leakage current and thereby extending the operating life of an integrated circuit (IC). A current sensitive voltage device such as a bipolar transistor or diode clamps the reverse-bias voltage of the base-emitter path. Voltage clamping prevents the bipolar transistors from activating while the buffer is disabled. The output leakage current that occurs when the junction is forward biased is minimized. This results in low output load capacitance that improves the propagation delay particularly when multiple buffers are used.

REFERENCES:
patent: 4490631 (1984-12-01), Kung
patent: 4701642 (1987-10-01), Pricer
patent: 5047669 (1991-09-01), Iwamura et al.
patent: 5107142 (1992-04-01), Bhamidipaty
patent: 5107143 (1992-04-01), Ueno et al.
patent: 5153464 (1992-10-01), Joly
patent: 5426377 (1995-06-01), Kimura

Affiliated with

Also associated with

Rating

BiCMOS tri-state buffer with low leakage current does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with BiCMOS tri-state buffer with low leakage current, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and BiCMOS tri-state buffer with low leakage current will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-142452