BiCMOS static memory with improved performance stability

Static information storage and retrieval – Systems using particular element – Semiconductive

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Details

365207, 365208, 365190, 307530, G11C 700, G11C 11407

Patent

active

050918796

ABSTRACT:
A BiCMOS static random access memory is disclosed, where the sense amplifiers each consist of a pair of bipolar transistors connected in emitter-coupled fashion. A pair of current sources, such as MOS transistors, are connected between the bases of said bipolar transistors and ground, to provide additional pull-down current for the bit lines. This additional pull-down current reduces the differential bit line voltage, improving the speed at which subsequent reads may be performed. Another embodiment uses a dummy column as a detection circuit, with the output of the dummy column controlling an operational amplifier, so that the operational amplifier may bias the current source pair to control the pull-down current, and thus the differential bit line voltage. Another embodiment controls the current source pair responsive to the row address, so that the effects of series bit line resistance may be taken into account in establishing the desired pull-down current.

REFERENCES:
patent: 4616342 (1986-10-01), Miyamoto
patent: 4646268 (1987-02-01), Kuno
patent: 4658159 (1987-04-01), Miyamoto
patent: 4665505 (1987-05-01), Miyakawa et al.
patent: 4910711 (1990-03-01), Guo
ISSCC 86 Session XVI; Static Ram's "A13ns/500 mw 64 kg ECL RAM", by Ogive et al., 2/20/86.
ISSCC 88 Session XIII, Static Ram's "A12ns 256 K Bi CMOS SRAM", by Kertis et al., 2/18/88.
IEEE Journal of Solid-State Circuits, vol. 23, No. 5, 10/88, Hiepvantran, et al.
"An 8-ns 256 K ECL SRAM with Memory Array CNOS & Battery Backup".
1988 IEEE International Solid-State Conference, Digest of Technical Papers, 1st. Ed., 2/88 "8-ns BICMOS 256K ECL. SRAM".

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