BICMOS sense circuit for sensing data during a read cycle of a m

Details BICMOS sense circuit for sensing data during a read cycle of a m BICMOS sense circuit for sensing data during a read cycle of a m

1990-09-04

1993-07-20

Dixon, Joseph L.

Static information storage and retrieval

Read/write circuit

Differential sensing

365177, 36518906, 36518909, 365190, 365203, 307495, 307530, G11C 1140

Patent

active

052299678

ABSTRACT:
A bipolar complementary metal oxide semiconductor (BICMOS) sense circuit for sensing data on read data lines during a read cycle of a memory comprises a load portion and a sense amplifier portion. In one form, the load portion couples true and complement read data lines to a first voltage in response to a start of a read cycle. When the true and complement read data lines exceed a predetermined voltage, the sense amplifier is enabled. The load portion becomes inactive when the voltage on the read data lines reaches approximately the first voltage. Then a selected memory cell provides a differential voltage on a bit line pair, which is coupled to the read data lines, indicating the contents of the selected memory cell. The sense amplifier provides a differential current onto a corresponding read global data line pair in response to the differential voltage. At the termination of the read cycle, the load portion becomes active again and couples the read data lines to a second voltage to disable the sense amplifier. The predetermined voltage is between the first voltage and the second voltage. The circuit increases the speed of the sensing function over a CMOS design, while keeping power consumption to a minimum. In another form, the sense circuit generates a read sense voltage that is substantially independent of non-tracking process variations between P-channel and N-channel field-effect transistors.

REFERENCES:
patent: 4740921 (1988-08-01), Lewandowski et al.
patent: 4802129 (1989-01-01), Hoekstra et al.
patent: 4821232 (1989-04-01), Nakano et al.
patent: 4829479 (1989-05-01), Mitsumoto et al.
patent: 4853899 (1989-08-01), Kitsukawa et al.
patent: 4866674 (1989-09-01), Tran
patent: 4899317 (1990-02-01), Hoekstra et al.
patent: 4928268 (1990-05-01), Nogle
patent: 4984207 (1991-01-01), Tateno et al.
patent: 4985864 (1991-01-01), Pice
patent: 5043945 (1991-08-01), Bader
patent: 5058067 (1991-10-01), Kertis
Tran et al., "An 8ns BICMOS 1Mb ECL SRAM with a Configurable Memory Array Size", 1989 IEEE Solid State Circuits Conference, pp. 36-37.
Kertis et al., "A 12ns 256K BICMOS SRAM", 1989 IEEE Solid State Circuits Conference, pp. 186-187.
Burnett and Hu, "Hot-Carrier Degradation in Bipolar Transistors at 300 and 110 K-Effect on BICMOS Inverter Performance", IEEE Transactions on Electron Devices, v. 37, No. 4, Apr. '90, pp. 1171-1172.
Odaka et al. "A 512kb/5ns BICMOS RAM with 1kG/150ps Logic Gate Array", 1989 IEEE Solid State Circuits Conference, pp. 28-29.

Affiliated with

Also associated with

Rating

BICMOS sense circuit for sensing data during a read cycle of a m does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with BICMOS sense circuit for sensing data during a read cycle of a m, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and BICMOS sense circuit for sensing data during a read cycle of a m will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1766212