BiCMOS semiconductor memory device using load transistors formed

Details BiCMOS semiconductor memory device using load transistors formed BiCMOS semiconductor memory device using load transistors formed

1992-06-09

1994-06-14

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Semiconductive

257370, 257378, 257517, H01L 21225

Patent

active

053216504

ABSTRACT:
P-channel MOSFETs in a fully CMOS-type memory cell are formed by a thin film (polysilicon), and portions that serve as source and drain regions of the thin-film p-channel MOSFETs are thickened by a conductor layer having a small resistance value. Further, the thin film and the conductor layer having a small resistance value are formed in common with a base lead-out layer of an npn bipolar transistor constituting a peripheral circuit.

REFERENCES:
patent: 4879255 (1989-11-01), Deguchi et al.
patent: 4892837 (1990-02-01), Kudo
patent: 4984200 (1991-01-01), Saitoo et al.
patent: 5065208 (1991-11-01), Shah et al.

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