Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2007-03-13
2008-12-16
Mandala, Victor A (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S565000, C257S370000, C257S632000
Reexamination Certificate
active
07466008
ABSTRACT:
A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.
REFERENCES:
patent: 5241214 (1993-08-01), Herbots et al.
patent: 6509587 (2003-01-01), Sugiyama et al.
patent: 6828211 (2004-12-01), Chi
patent: 7081395 (2006-07-01), Chi et al.
patent: 2004/0232513 (2004-11-01), Chi et al.
patent: 2007/0181977 (2007-08-01), Lochtefeld et al.
patent: 2007/0252230 (2007-11-01), Zhu et al.
patent: 2007/0267723 (2007-11-01), Bernstein et al.
Creemer, J. F., et al., “A new model of the effect of mechanical stress on the saturation current of bipolar transistors,” Sensors and Actuators A 97-98, Elsevier Science, 2002, pp. 289-295.
Gallon, C., et al., “Electrical Analysis of External Mechanical Stress Effects in Short Channel MOSFETs on (001) Silicon,” Solid-State Electronics 48, Elsevier Science, vol. 48, 2004, pp. 561-566.
Thompson, S. E., et al., “A 90-nm Logic Technology Featuring Strained-Silicon,” IEEE Transactions On Electron Devices, vol. 51, No. 11, Nov. 2004, pp. 1790-1797.
Thompson, S. E., et al., “Key Differences For Process-induced Uniaxial vs. Substrate-induced Biaxial Stressed Si and Ge Channel MOSFETs,” IEEE, Dec. 2004, pp. 221-224.
Yuan, F., et al., “Mechanically Strained Si-SiGe HBTs,” IEEE Electron Device Letters, vol. 25, No. 7, Jul. 2004, pp. 483-485.
Yang, H. S., et al., “Dual Stress Liner for High Performance sub-45nm Gate Length SOI CMOS Manufacturing,” IEEE, Dec. 2004, pp. 1075-1077.
Chen Hung-Wei
Ke Chung-Hu
Ko Chih-Hsin
Lee Wen-Chin
Wang Tzu-Juei
Mandala Victor A
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
BiCMOS performance enhancement by mechanical uniaxial strain... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with BiCMOS performance enhancement by mechanical uniaxial strain..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and BiCMOS performance enhancement by mechanical uniaxial strain... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4030467