BiCMOS memory having memory cells connected directly to address

Details BiCMOS memory having memory cells connected directly to address BiCMOS memory having memory cells connected directly to address

1990-08-17

1991-09-10

Bowler, Alyssa H.

Static information storage and retrieval

Systems using particular element

Semiconductive

365190, 307446, 357 43, G11C 1136, G11C 11407

Patent

active

050479806

ABSTRACT:
A digital BiCMOS memory chip includes a row of memory cells, and an addressing circuit for the row of cells. Each of the memory cells is constructed of field-effect transistors which operate at CMOS voltage levels, whereas the address decorder is constructed of bipolar transistors which operate at ECL voltage levels. A direct connection is made via a row line from the address decoder to the row of memory cells with no ECL-to-CMOS voltage level converter lying there between. This direct connection is made operable by properly selecting all voltages that occur on certain nodes in the address decoder and the memory cell. And, it enables the memory to be read faster plus occupy less chip space and dissipate less power than the prior art.

REFERENCES:
patent: 4858183 (1989-08-01), Scharrer et al.
patent: 4866673 (1989-09-01), Higuchi et al.
patent: 4961170 (1990-10-01), Maki et al.

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