BiCMOS inverter

Details BiCMOS inverter BiCMOS inverter

2002-01-18

2004-07-13

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S369000, C257S370000, C326S110000, C327S112000

Reexamination Certificate

active

06762465

ABSTRACT:

Applicant hereby incorporates by reference U.S. patent application Ser. No. 10/050,792, filled Jan. 18, 2002, in its entirety.
TECHNICAL FIELD
The present invention includes semiconductor devices including a plurality of switch elements each having a field effect transistor and a bi-polar transistor, and methods for manufacturing the same.
RELATED ART
A MOS field effect transistor with an SOI structure can be driven at a low power consumption and at a higher speed compared to an ordinary MOS field effect transistor.
FIG. 26
schematically shows one example of a MOS field effect transistor with an SOI structure. An embedded oxide film
1100
that is formed from a silicon oxide film is formed on a silicon substrate
2000
. A source region
1200
and a drain region
1300
are formed on the embedded oxide film
1100
. A body region
1400
is formed on the embedded oxide film
1100
and between the source region
1200
and the drain region
1300
. A gate electrode
1500
is formed on the body region
1400
through a gate dielectric layer.
It is noted that the body region
1400
of the MOS field effect transistor is in a floating state. Accordingly, carriers that are generated by an impact ionization phenomenon are stored in the body region
1400
. When carriers are stored in the body region
1400
, the potential of the body region
1400
changes. A phenomenon that is a so-called substrate floating effect takes place. When the substrate floating effect occurs, a kink phenomenon and a history effect occur in the MOS field effect transistor.


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Silicon Processing for the VLSI Era, Wolf. Stanley. Lattice Press. 1990. vol. II. pp. 557-558.*
SOI bipolar-MOS merged transistors for BiCMOS application: Zheng et al.. Electronics Letters, vol. 35 Issue 14. Jul. 8, 1999 pp. 1203-1204.*
U.S. application Ser. No. 10/050,792, filed Jan.18, 2002, having U.S. patent application Pub. No. U.S. 2002/0153575 A1, published Oct. 24, 2002.
U.S. application Ser. No. 10/014,612, filed Dec. 14, 2001, having U.S. patent application Pub. No. U.S. 2002/0117721 A, published Aug. 29, 2002.
Notice of Reasons of Rejection for Japanese Patent Application No. 2001-011859 (from which priority is claimed in U.S. Ser. No. 10/050,793), which cites JP05-041488 and JP05-218316.
Notice of Reasons of Rejection for Japanese Patent Application No. 2001-011858 (from which priority is claimed in U.S. Ser. No. 10/050,792), which cites JP05-041488 and JP05-218316, which were previously cited in an IDS.
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Parke et al., “Bipolar-FET Hybrid-Mode Operation of Quarter-Micrometer SOI MOSFET's,”IEEE Electron Device Letters, vol. 14, No. 5, May 1993, pp. 234-236.

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