BICMOS combined bit line load and write gate for a memory

Details BICMOS combined bit line load and write gate for a memory BICMOS combined bit line load and write gate for a memory

1990-12-10

1992-12-22

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

For complementary information

365203, 365177, G11C 700

Patent

active

051738775

ABSTRACT:
A BICMOS combined bit line load and write gate for a memory comprises first and second portions coupled to first and second bit lines of a bit line pair, the first and second portions each comprising first through sixth transistors. The first and second transistors are serially coupled from a power supply voltage terminal to form a CMOS inverter whose input terminal receives a local write signal and whose output terminal is coupled to the base of the fifth transistor. The third transistor has a drain coupled to the source of the second transistor, a gate for receiving the local write signal, and a source for receiving a data signal. The fourth transistor is serially coupled between the base of the fifth transistor and the source of the third transistor, with the local write signal coupled to the gate thereof. The fifth transistor has a collector coupled to the power supply voltage terminal, and an emitter coupled to a corresponding bit line. The sixth transistor receives the local write signal and is serially coupled between the power supply voltage terminal and the corresponding bit line. The BICMOS combined bit line load and write gate prevents failure due to the body effect, avoids failure due to manufacturing variations which occur due to ratioing of transistors, provides the ability to adapt the memory to different data organizations, and prevents of self boosting of the base of the fifth transistor.

REFERENCES:
patent: 4402066 (1983-08-01), Itoh et al.
patent: 4730279 (1988-03-01), Ohtani
patent: 4866674 (1989-09-01), Tran
patent: 4926383 (1990-05-01), Kertis
patent: 5058067 (1991-10-01), Kertis
Tran et al., "An 8ns BiCMOS 1Mb ECL SRAM with a Configurable Memory Array Size", 1989 IEEE Solid State Circuits Conference, pp. 36-37.
Kertis et al., "A 12ns 256K BiCMOS SRAM", 1989 IEEE Solid State Circuits Conf., pp. 186-187.
Burnett and Hu, "Hot-Carrier Deg. in Bipol. Trans. at 300 and 110 K-Eft. on BiCMOS Inver. Perf.", IEEE Transactions on Electron Devices, vol. 37, No. 4, Apr. 1990, pp. 1171-1173.

Affiliated with

Also associated with

Rating

BICMOS combined bit line load and write gate for a memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with BICMOS combined bit line load and write gate for a memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and BICMOS combined bit line load and write gate for a memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-978508