BiCMOS circuit for translation of ECL logic levels to MOS logic

Details BiCMOS circuit for translation of ECL logic levels to MOS logic BiCMOS circuit for translation of ECL logic levels to MOS logic

1993-07-01

1995-10-17

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326 32, H03K 190175

Patent

active

054594120

ABSTRACT:
A translator circuit for converting from a first logic-level range to a second logic-level range, as is generally involved in the translation from an ECL stage to a CMOS stage. The translator includes a reference stage that provides a reference voltage that is coupled to the CMOS logic stage as well as the ECL logic stage. The ECL logic stage is indirectly coupled between a high potential power rail and a low potential power rail through a plurality of transistors. The CMOS stage is coupled to the ECL stage through two emitter-follower transistors. The CMOS stage uses current-mirroring techniques in combination with the isolated reference stage to effect a translation from the ECL logic level to the CMOS logic level. The CMOS stage also provides relatively fast propagation time which may be set, within certain limits, to a desired time. The reference stage provides an output signal to the gates of the transistors of the CMOS stage through a bipolar transistor that minimizes impedance and isolates the reference stage from switching noise. Use of the bipolar transistor in the reference stage permits fan out to a plurality of output stages through the use of a single reference stage of the present invention.

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