BICMOS cache TAG having small signal exclusive OR for TAG compar

Details BICMOS cache TAG having small signal exclusive OR for TAG compar BICMOS cache TAG having small signal exclusive OR for TAG compar

1994-09-15

1995-09-05

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including signal comparison

365 49, 36518911, G11C 1500

Patent

active

054485231

ABSTRACT:
A cache TAG RAM (25) includes a TAG array (26), a small signal exclusive OR logic circuit (33, 34), a sense amplifier (36, 37), and another exclusive OR logic circuit (30, 31). A comparison of a stored TAG address to the input address signal is made by the small signal exclusive OR logic circuit (33, 34) to provide a hit signal very quickly. The stored TAG address that is lost during the exclusive OR operation is recovered by performing another exclusive OR on the match information and the input address signal. By using a small signal exclusive OR circuit to perform a comparison early, the hit signal can be generated very quickly.

REFERENCES:
patent: 5218567 (1993-06-01), Suzuki et al.
patent: 5241510 (1993-08-01), Kobayashi et al.
patent: 5253197 (1993-10-01), Suzuki et al.
patent: 5329632 (1994-07-01), Lee et al.

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